Datasheet

REV. 0
AD7650
–4–
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
REFER TO FIGURES 13 AND 14 (continued)
SCLK Last Edge to SYNC Delay t
24
3
CS HIGH to SYNC HI-Z t
25
10 ns
CS HIGH to Internal SCLK HI-Z t
26
10 ns
CS HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read After Convert t
28
2.75/3/3.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to SYNC Asserted Delay t
29
1/1.25/1.5 µs
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay t
30
50 ns
REFER TO FIGURES 15 AND 16
(Slave Serial Interface Modes)
2
External SCLK Setup Time t
31
5ns
External SCLK Active Edge to SDOUT Delay t
32
316ns
SDIN Setup Time t
33
5ns
SDIN Hold Time t
34
5ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
NOTES
1
In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
(continued)
I
OH
500␮A
1.6mA
I
OL
TO OUTPUT
PIN
1.4V
C
L
60pF*
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C
L
= 10 pF
0.8V
2V
2V
0.8V
0.8V
2V
t
DELAY
t
DELAY
Figure 2. Voltage Reference Levels for Timing