Datasheet

REV. 0
AD7650
–16–
SCLK
SDOUT
D15 D14 D1
D0
D13
X15 X14 X13 X1 X0 Y15 Y14
CS
BUSY
SDIN
EXT/INT = 1 INVSCLK = 0
t
35
t
36
t
37
t
31
t
32
t
16
t
33
X15 X14
X
1 2 3 14151617 18
RD = 0
t
34
Figure 15. Slave Serial Data Timing for Reading (Read After Convert)
SDOUT
CS
SCLK
D1
D0
X
D15 D14 D13
123 141516
t
3
t
35
t
36
t
37
t
31
t
32
t
16
CNVST
BUSY
EXT/INT = 1 INVSCLK = 0
RD = 0
Figure 16. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
SCLK
SDOUTRDC/SDIN
BUSYBUSY
DATA OUT
AD7650
#1
(DOWNSTREAM)
BUSY OUT
CNVST
CS
SCLK
AD7650
#2
(UPSTREAM)
RDC/SDIN SDOUT
SCLK IN
CS IN
CNVST IN
CNVST
CS
Figure 17. Two AD7650s in a “Daisy-Chain” Configuration
External Clock Data Read During Conversion
Figure 16 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are both low, the
result of the previous conversion can be read. The data is shifted
out, MSB first, with 16 clock pulses and is valid on both rising
and falling edge of the clock. The 16 bits have to be read before the
current conversion is complete. If that is not done, RDERROR
is pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no “daisy chain”
feature in this mode and RDC/SDIN input should always be tied
either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of, at least 18 MHz, when impulse mode is
used, 25 MHz when normal mode is used or 40 MHz when
warp mode is used, is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue to
read the last bits even after a new conversion has been initiated.
That allows the use of a slower clock speed like 14 MHz in impulse
mode, 18 MHz in normal mode and 25 MHz in warp mode.