Datasheet

AD7643
Rev. 0 | Page 6 of 28
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t
18
1 3 3 3 ns
Internal SCLK Period Minimum t
19
8 16 32 64 ns
Internal SCLK Period Maximum t
19
20 40 70 135 ns
Internal SCLK High Minimum t
20
2 8 16 32 ns
Internal SCLK Low Minimum t
21
2 8 16 32 ns
SDOUT Valid Setup Time Minimum t
22
1 5 5 5 ns
SDOUT Valid Hold Time Minimum t
23
0 0.5 10 30 ns
SCLK Last Edge to SYNC Delay Minimum t
24
0 0.5 9 26 ns
BUSY High Width Maximum t
28
0.84 1.14 1.72 2.88 μs
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
500µA I
OL
500µA I
OH
1.4V
TO OUTPUT
PIN
C
L
50pF
0
6024-002
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, C
L
= 10 pF
0.8V
2V
2V
0.8V
0.8V
2V
t
DELAY
t
DELAY
0
6024-003
Figure 3. Voltage Reference Levels for Timing