Datasheet

AD7643
Rev. 0 | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
REF
= 2.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 30 and Figure 31)
Convert Pulse Width t
1
15 70
1
ns
Time Between Conversions t
2
800 ns
CNVST
Low to BUSY High Delay
t
3
23 ns
BUSY High All Modes (Except Master Serial Read After Convert) t
4
550 ns
Aperture Delay t
5
1 ns
End of Conversion to BUSY Low Delay t
6
10 ns
Conversion Time t
7
550 ns
Acquisition Time t
8
250 ns
RESET Pulse Width t
9
15 ns
RESET Low to BUSY High Delay
2
t
38
10 ns
BUSY High Time from RESET Low
2
t
39
500 ns
PARALLEL INTERFACE MODES (Refer to Figure 32 to Figure 35 )
CNVST
Low to Data Valid Delay
t
10
550 ns
Data Valid to BUSY Low Delay t
11
2 ns
Bus Access Request to Data Valid t
12
20 ns
Bus Relinquish Time t
13
2 15 ns
MASTER SERIAL INTERFACE MODES
3
(Refer to Figure 36 and Figure 37)
CS
Low to SYNC Valid Delay
t
14
10 ns
CS
Low to Internal SCLK Valid Delay
3
t
15
10 ns
CS
Low to SDOUT Delay
t
16
10 ns
CNVST
Low to SYNC Delay
t
17
135 ns
SYNC Asserted to SCLK First Edge Delay t
18
2 ns
Internal SCLK Period
4
t
19
8 20 ns
Internal SCLK High
4
t
20
2 ns
Internal SCLK Low
4
t
21
2 ns
SDOUT Valid Setup Time
4
t
22
1 ns
SDOUT Valid Hold Time
4
t
23
0 ns
SCLK Last Edge to SYNC Delay
4
t
24
0 ns
CS
High to SYNC Hi-Z
t
25
10 ns
CS
High to Internal SCLK Hi-Z
t
26
10 ns
CS
High to SDOUT Hi-Z
t
27
10 ns
BUSY High in Master Serial Read After Convert
4
t
28
See Table 4 ns
CNVST
Low to SYNC Asserted Delay
t
29
508 ns
SYNC Deasserted to BUSY Low Delay t
30
13 ns
SLAVE SERIAL INTERFACE MODES (Refer to Figure 39 and Figure 40)
External SCLK Set-Up Time t
31
5 ns
External SCLK Active Edge to SDOUT Delay t
32
1 8 ns
SDIN Set-Up Time t
33
5 ns
SDIN Hold Time t
34
5 ns
External SCLK Period t
35
12.5 ns
External SCLK High t
36
5 ns
External SCLK Low t
37
5 ns
1
See the Conversion Control section.
2
See the Digital Interface section and the RESET section.
3
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
4
In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.