Datasheet

AD7643
Rev. 0 | Page 23 of 28
BUSY
SYNC
SCLK
S
DOUT
123 161718
D17 D16 D2 D1 D0
X
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
CNVST
CS, RD
EXT/INT = 0
t
23
t
22
t
16
t
15
t
14
t
29
t
19
t
21
t
20
t
18
t
28
t
30
t
24
t
25
t
26
t
27
t
3
DIVSCLK[1:0] = 0
06024-036
Figure 36. Master Serial Data Timing for Reading (Read After Convert)
EXT/INT = 0
RDC/SDIN = 1 INVSCLK = INVSYNC = 0
D17 D16 D2 D1 D0X
123 161718
BUSY
SYNC
SCLK
SDOUT
CNVST
CS, RD
t
23
t
18
t
15
t
14
t
17
t
3
t
22
t
16
t
1
t
25
t
26
t
24
t
27
t
19
t
20
t
21
0
6024-037
Figure 37. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)