Datasheet

AD7643
Rev. 0 | Page 21 of 28
INTERFACES
DIGITAL INTERFACE
The AD7643 has a versatile digital interface that can be set up
as either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7643
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic
with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic
high output voltage. In most applications, the OVDD supply pin
of the AD7643 is connected to the host system interface 2.5 V
or 3.3 V digital supply. By using the D0/OB/
2C
input pin, either
twos complement or straight binary coding can be used.
The two signals
CS
and
RD
control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually,
CS
allows the selection of each AD7643 in
multicircuit applications and is held low in a single AD7643
design.
RD
is generally used to enable the conversion result on
the data bus.
RESET
The RESET input is used to reset the AD7643 and generate a
fast initialization. A rising edge on RESET aborts the current
conversion (if any) and tristates the data bus. The falling edge of
RESET clears the data bus and engages the initialization process
indicated by pulsing BUSY high. Conversions can take place
after the falling edge of BUSY. Refer to
Figure 31 for the RESET
timing details.
RESET
DATA
BUSY
CNVST
t
38
t
39
t
8
t
9
06024-031
Figure 31. RESET Timing
PARALLEL INTERFACE
The AD7643 is configured to use the parallel interface for an
18-bit, 16-bit, or 8-bit bus width according to
Table 7.
Master Parallel Interface
Data can be continuously read by tying
CS
and
RD
low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications, unless the device is held in RESET.
Figure 32 details the timing for this mode.
t
1
BUSY
DATA
BUS
PREVIOUS CONVERSION DATA NEW DATA
CNVST
CS = RD = 0
t
10
t
4
t
11
t
3
06024-032
Figure 32. Master Parallel Data Timing for Reading (Continuous Read)
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in
Figure 33 and
Figure 34, respectively. When the data is read during the
conversion, it is recommended that it is read-only during the
first half of the conversion phase. This avoids any potential
feedthrough between voltage transients on the digital interface
and the most critical analog conversion circuitry.
CURRENT
CONVERSION
t
13
t
12
BUSY
DATA
BUS
RD
CS
06024-033
Figure 33. Slave Parallel Data Timing for Reading (Read After Convert)
PREVIOUS
CONVERSION
t
13
t
12
t
3
BUSY
DATA
BUS
CNVST,
RD
CS = 0
t
4
t
1
06024-034
Figure 34. Slave Parallel Data Timing for Reading (Read During Convert)