Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LQFP 48

18-Bit, 1.25 MSPS PulSAR

ADC

AD7643

Rev. 0

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FEATURES

Throughput: 1.25 MSPS

INL: ±1.5 LSB typical, ±3 LSB maximum (±11 ppm of full scale)

18-bit resolution with no missing codes

Dynamic range:

95 dB typical

SINAD:

93.5 dB typical @ 20 kHz (V

REF

= 2.5 V)

THD:

−113 dB typical @ 20 kHz (V

REF

= 2.5 V)

2.048 V internal reference: typical drift

8 ppm/°C; TEMP output

Differential input range: ±V

REF

up to 2.5 V)

No pipeline delay (SAR architecture)

Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface

SPI®/QSPI™/MICROWIRE™/DSP compatible

Single 2.5 V supply operation

Power dissipation

65 mW typical @ 1.25 MSPS with internal REF

2 μW in power-down mode

Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ

Pin compatible with the

AD7641 and other PulSAR ADC’s

APPLICATIONS

Medical instruments

High speed data acquisition/high dynamic data acquisition

Digital signal processing

Spectrum analysis

Instrumentation

Communications

ATE

GENERAL DESCRIPTION

The AD7643 is an 18-bit, 1.25 MSPS, charge redistribution

SAR, fully differential, analog-to-digital converter (ADC) that

operates from a single 2.5 V power supply. The part contains a

high speed, 18-bit sampling ADC, an internal conversion clock,

an internal reference (and buffer), error correction circuits, and

both serial and parallel system interface ports. The part has no

latency and can be used in asynchronous rate applications. The

AD7643 is hardware factory calibrated and tested to ensure ac

parameters, such as signal-to-noise ratio (SNR), in addition to

the more traditional dc parameters of gain, offset, and linearity.

The AD7643 is only available in Pb-free packages with

operation specified from −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

CLOCK

AD7643

DGNDDVDD

AVDD

AGND

REF REFGND

IN+

IN–

RESET

PDBUF

REFBUFIN

PDREF

REF

TEMP

D[17:0]

BUSY

D0/OB/2C

OGND

OVDD

MODE1

MODE0

REF AMP

CNVST

SERIAL

PORT

PARALLEL

INTERFACE

SWITCHED

CAP DAC

06024-001

Figure 1.

Table 1. PulSAR 48-Lead Selection

Type/kSPS

100 to

250

500 to

570

650 to

1000

>1000

Pseudo

Differential

AD7651,

AD7660,

AD7661

AD7650,

AD7652,

AD7664,

AD7666

AD7653,

AD7667

True Bipolar

AD7610,

AD7663

AD7665

AD7612,

AD7671

True

Differential

AD7675 AD7676 AD7677

AD7621,

AD7622,

AD7623

18-Bit

Multichannel/

AD7631,

AD7678

AD7679

AD7634,

AD7674

AD7641,

AD7643

Simultaneous AD7654 AD7655

PRODUCT HIGHLIGHTS

1. Fast Throughput.

The AD7643 is a

1.25 MSPS, charge redistribution,

18-bit SAR ADC.

2. Superior Linearity.

The AD7643 has no missing 18-bit code.

3. Internal Reference.

The AD7643 has a 2.048 V internal reference with a typical

drift of ±

8 ppm/°C and an on-chip TEMP sensor.

4. Single-Supply Operation.

The AD7643 operates from a 2.5 V single supply.

5. Serial or Parallel Interface.

Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial

interface arrangement compatible with 2.5 V, 3.3 V, or

5 V logic.

Summary of content (28 pages)

PAGE 1
8-Bit, 1.25 MSPS PulSAR® ADC AD7643 FEATURES APPLICATIONS Medical instruments High speed data acquisition/high dynamic data acquisition Digital signal processing Spectrum analysis Instrumentation Communications ATE GENERAL DESCRIPTION The AD7643 is an 18-bit, 1.25 MSPS, charge redistribution SAR, fully differential, analog-to-digital converter (ADC) that operates from a single 2.5 V power supply.
PAGE 2
AD7643 TABLE OF CONTENTS Features .............................................................................................. 1 Multiplexed Inputs ..................................................................... 17 Applications....................................................................................... 1 Driver Amplifier Choice ........................................................... 18 General Description .........................................................................
PAGE 3
AD7643 SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 4
AD7643 Parameter Turn-On Settling Time REFBUFIN Output Voltage REFBUFIN Output Resistance EXTERNAL REFERENCE Voltage Range Current Drain REFERENCE BUFFER REFBUFIN Input Voltage Range REFBUFIN Input Current TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format 7 Pipeline Delay 8 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current 10 AVDD 11 DVDD OVDD12 Power Dissipation10, 11 With Internal Ref
PAGE 5
AD7643 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
PAGE 6
AD7643 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK High Minimum Internal SCLK Low Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum BUSY High Width Maximum 500µA 0 0 1 8 20 2 2 1 0 0 0.84 0 1 3 16 40 8 8 5 0.5 0.5 1.14 1 0 3 32 70 16 16 5 10 9 1.72 1 1 3 64 135 32 32 5 30 26 2.
PAGE 7
AD7643 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs/Outputs IN+ 1 , IN−, REF, REFBUFIN, TEMP, INGND, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD OVDD AVDD to DVDD AVDD, DVDD to OVDD Digital Inputs PDREF, PDBUF 2 Internal Power Dissipation 3 Internal Power Dissipation 4 Junction Temperature Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 8
AD7643 REFGND REF IN– AGND NC IN+ AGND AVDD PDBUF PDREF REFBUFIN TEMP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 AGND CNVST MODE0 3 MODE1 4 34 PD 33 D0/OB/2C 5 32 RESET CS 31 RD 30 29 DGND BUSY D2/A1 9 D3 10 28 D17 27 D16 D4/DIVSCLK[0] 11 D5/DIVSCLK[1] 12 26 D15 D14 PIN 1 IDENTIFIER AD7643 DGND 6 TOP VIEW (Not to Scale) DGND 7 D1/A0 8 D13/RDERROR D11/SCLK D12/SYNC DVDD DGND D10/SDOUT OVDD D9/RDC/SDIN OGND 13 14 15 16 17 18 19 2
PAGE 9
AD7643 Pin No. 14 Mnemonic D7 or INVSYNC Type 1 DI/O 15 D8 or INVSCLK DI/O 16 D9 or RDC DI/O or SDIN 17 18 OGND OVDD P P 19 20 21 DVDD DGND D10 or SDOUT P P DO 22 D11 or SCLK DI/O 23 D12 or SYNC DO 24 D13 or RDERROR DO 25 to 28 29 D[14:17] DO BUSY DO 30 DGND P Description When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), invert sync select.
PAGE 10
AD7643 Pin No. 31 Mnemonic RD Type 1 DI Description Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. 32 CS DI 33 RESET DI 34 PD DI 35 CNVST DI 37 REF AI/O 38 39 40 43 45 REFGND IN− NC IN+ TEMP AI AI 46 REFBUFIN AI/O 47 PDREF DI 48 PDBUF DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode. Reset Input.
PAGE 11
AD7643 TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.
PAGE 12
AD7643 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 1.25 2.5 1.0 2.0 1.5 0.5 0.5 DNL (LSB) INL (LSB) 1.0 0 –0.5 0 –1.0 –1.5 –0.5 –2.0 0 65536 131072 262144 196608 –1.0 06024-005 CODE 0 65536 Figure 5. Integral Nonlinearity vs. Code 40000 35000 35000 COUNTS 17320 15000 20000 18613 16141 15505 15000 13376 10173 10000 20038 20037 20036 20034 20033 20032 20031 20030 2002F 2002E 2002D 2002C CODE IN HEX Figure 6.
PAGE 13
AD7643 0 –20 SNR = 93.4dB THD = –113dB SFDR = 108dB SINAD = 93.4dB –40 –60 –80 –100 –120 –140 SNR = 93dB THD = –106dB SFDR = 109dB SINAD = 92.8dB –40 –60 –80 –100 –120 –140 –160 400 600 500 –180 FREQUENCY (kHz) 0 100 200 95 16.0 93 15.6 14.0 83 13.6 81 13.2 79 12.8 77 12.4 12.
PAGE 14
AD7643 100k AVDD 10k OPERATING CURRENTS (µA) 95.5 95.0 SNR 94.5 SINAD 94.0 1k DVDD 100 OVDD = 3.3V 10 1 OVDD = 2.5V 93.5 0.1 –50 –40 –30 –20 0 –10 INPUT LEVEL (dB) 0.01 10 1k 10k 100k 10M 1M SAMPLING RATE (SPS) Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 19. Operating Current vs. Sampling Rate 16 20 14 18 12 16 OVDD = 2.5V @ 85°C t12 DELAY (ns) OVDD = 2.5V @ 25°C 10 DVDD 8 OVDD, 3.3V 6 14 12 10 OVDD = 3.3V @ 25°C OVDD, 2.
PAGE 15
AD7643 APPLICATIONS INFORMATION IN+ AGND LSB MSB 131,072C 65,536C 4C 2C C SW+ SWITCHES CONTROL C BUSY REF COMP REFGND 4C 2C MSB C OUTPUT CODE C SW– LSB AGND IN– CNVST 06024-021 131,072C 65,536C CONTROL LOGIC Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7643 is a very fast, low power, single-supply, precise 18-bit ADC using successive approximation architecture. The AD7643 is capable of converting 1,250,000 samples per second (1.25 MSPS).
PAGE 16
AD7643 TRANSFER FUNCTIONS Table 8. Output Codes and Ideal Input Voltages Description FSR −1 LSB FSR − 2 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 111...111 111...110 111...101 1 2 000...010 000...001 000...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB Analog Input VREF = 2.048 V +2.0479844 V +2.0479688 V +15.625 μV 0V −15.625 μV −2.0479844 V −2.
PAGE 17
AD7643 TYPICAL CONNECTION DIAGRAM Figure 23 shows a typical connection diagram for the AD7643. Different circuitry shown in this diagram is optional and is discussed in the following sections. ANALOG INPUTS Figure 24 shows an equivalent circuit of the input structure of the AD7643. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.
PAGE 18
AD7643 The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an NPO ceramic or mica type. Moreover, the use of a noninverting 1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio.
PAGE 19
AD7643 To use the internal reference, the PDREF and PDBUF inputs must both be low. This produces a 1.2 V band gap output on REFBUFIN, which is amplified by the internal buffer and results in a 2.048 V reference on the REF pin. The internal reference is temperature compensated to 2.048 V ± 10 mV. The reference is trimmed to provide a typical drift of 8 ppm/°C. This typical drift characteristic is shown in Figure 7. The output resistance of REFBUFIN is 6.33 kΩ (minimum) when the internal reference is enabled.
PAGE 20
AD7643 POWER SUPPLY The AD7643 uses three sets of power supply pins: an analog 2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.3 V and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 23.
PAGE 21
AD7643 INTERFACES DIGITAL INTERFACE CS = RD = 0 The AD7643 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The serial interface is multiplexed on the parallel data bus. The AD7643 digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic high output voltage. In most applications, the OVDD supply pin of the AD7643 is connected to the host system interface 2.5 V or 3.
PAGE 22
AD7643 16-Bit and 8-Bit Interface (Master or Slave) MASTER SERIAL INTERFACE In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2) interfaces, the A0/A1 pins allow a glueless interface to a 16- or 8-bit bus, as shown in Figure 35. By connecting A0/A1 to an address line(s), the data can be read in two words for a 16-bit interface, or three bytes for an 8-bit interface. This interface can be used in both master and slave parallel reading modes. Refer to Table 7 for the full details of the interface.
PAGE 23
AD7643 EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 DIVSCLK[1:0] = 0 CS, RD t3 CNVST t28 BUSY t30 t29 t25 SYNC t18 t19 t14 t20 1 2 D17 D16 SCLK t24 t21 3 16 17 D2 D1 t26 18 t15 t27 X t16 D0 06024-036 SDOUT t23 t22 Figure 36.
PAGE 24
AD7643 SLAVE SERIAL INTERFACE The AD7643 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or a discontinuous clock.
PAGE 25
AD7643 RD = 0 INVSCLK = 0 EXT/INT = 1 CS BUSY t35 t36 t37 SCLK 1 2 t31 3 16 17 18 19 20 t32 X SDOUT D17 t16 D16 D15 D1 D0 X17 X16 X16 X15 X1 X0 Y17 Y16 SDIN X17 t33 06024-039 t34 Figure 39. Slave Serial Data Timing for Reading (Read After Convert) t31 EXT/INT = 1 RD = 0 INVSCLK = 0 CS t3 CNVST t35 BUSY t36 SCLK t37 2 1 4 3 16 17 18 t32 X D17 D16 D15 D2 D1 D0 06024-040 SDOUT t16 Figure 40.
PAGE 26
AD7643 MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) The AD7643 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD7643 is designed to interface with a parallel 8-bit or 16-bit wide interface or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7643 to prevent digital noise from coupling into the ADC.
PAGE 27
AD7643 APPLICATION HINTS LAYOUT While the AD7643 has very good immunity to noise on the power supplies, exercise care with the grounding layout. To facilitate the use of ground planes that can be easily separated, design the printed circuit board that houses the AD7643 so that the analog and digital sections are separated and confined to certain areas of the board. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7643, or as close as possible to the AD7643.
PAGE 28
AD7643 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 48 1 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 13 12 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 0.60 MAX PADDLE CONNECTED TO AGND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 42.