Datasheet

AD7641
Rev. 0 | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
MODE0
MODE1
D0/OB/2C
NC = NO CONNECT
D1/A0
D2/A1
D3
D4/DIVSCLK[0]
BUSY
D17
D16
D15
AD7641
D5/DIVSCLK[1]
D14
D6/EXT/INT
D7/INVSYNC
D8/INVSCLK
D9/RDC/SDIN
OGND
OVDD
DVDD
DGND
D10/SDOUT
D11/SCLK
D12/SYNC
D13/RDERROR
PDBUF PDREF REFBUFIN TEMP AVDD IN+ AGND AGND NC IN– REFGND REF
WARP
04761-004
NORMAL
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin
No.
Mnemonic Type
1
Description
1, 36,
41, 42
AGND P Analog Power Ground Pin.
2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V.
3, 4 MODE[0:1] DI Data Output Interface Mode Selection.
Interface MODE# MODE1 MODE0 Description
0 0 0 18-bit interface
1 0 1 16-bit interface
2 1 0 8-bit (byte) interface
3 1 1 Serial interface
5
D0/OB/
2C
DI/O
When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus
and the data coding is straight binary. In all other modes, this pin allows the choice of straight
binary/twos complement. When OB/
2C
is high, the digital output is straight binary; when low,
the MSB is inverted resulting in a twos complement output from its internal shift register.
6 WARP DI
Conversion Mode Selection. When WARP = high and
NORMAL = high, this selects wideband warp
mode with slightly improved linearity and THD. When WARP = high and
NORMAL = low, this selects
warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and
a minimum conversion rate must be applied to guarantee full specified accuracy.
7
NORMAL
DI
Conversion Mode Selection. When
NORMAL = low and WARP = low, this input selects normal mode
where full accuracy is maintained independent of the minimum conversion rate.
8 D1/A0 DI/O
When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this
input pin controls the form in which data is output as shown in
Table 7.
9 D2/A1 DI/O When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus.
When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in
Table 7.
10 D3 D0
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus.
This pin is always an output, regardless of the interface mode.
11, 12 D[4:5] DI/O When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
or DIVSCLK[0:1]
When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read
after convert mode (EXT/
INT = low, RDC/SDIN = low), these inputs can be used to slow down the
internally generated serial clock that clocks the data output. In other serial modes, these pins are
high impedance outputs.