Datasheet

AD7641
Rev. 0 | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
REF
= 2.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 29 and Figure 30)
Convert Pulse Width t
1
15 70
1
ns
Time Between Conversions (Warp Mode
2
/Normal Mode
3
) t
2
500/667 ns
CNVST
Low to BUSY High Delay
t
3
23 ns
BUSY High All Modes (Except Master Serial Read After Convert) t
4
385/520 ns
Aperture Delay t
5
1 ns
End of Conversion to BUSY Low Delay t
6
10 ns
Conversion Time (Warp Mode/Normal Mode) t
7
385/520 ns
Acquisition Time (Warp Mode/Normal Mode) t
8
115 ns
RESET Pulse Width t
9
15 ns
RESET Low to BUSY High Delay
4
t
38
10 ns
BUSY High Time from RESET Low
4
t
39
600 ns
PARALLEL INTERFACE MODES (Refer to Figure 31 to Figure 34 )
CNVST
Low to Data Valid Delay (Warp Mode/Normal Mode)
t
10
385/520 ns
Data Valid to BUSY Low Delay t
11
2 ns
Bus Access Request to Data Valid t
12
20 ns
Bus Relinquish Time t
13
2 15 ns
MASTER SERIAL INTERFACE MODES
5
(Refer to Figure 35 and Figure 36)
CS
Low to SYNC Valid Delay
t
14
10 ns
CS
Low to Internal SCLK Valid Delay
5
t
15
10 ns
CS
Low to SDOUT Delay
t
16
10 ns
CNVST
Low to SYNC Delay (Warp Mode/Normal Mode)
t
17
14/137 ns
SYNC Asserted to SCLK First Edge Delay t
18
0.5 ns
Internal SCLK Period
6
t
19
8 14 ns
Internal SCLK High
6
t
20
2 ns
Internal SCLK Low
6
t
21
3 ns
SDOUT Valid Setup Time
6
t
22
1 ns
SDOUT Valid Hold Time
6
t
23
0 ns
SCLK Last Edge to SYNC Delay
6
t
24
0 ns
CS
High to SYNC HI-Z
t
25
10 ns
CS
High to Internal SCLK HI-Z
t
26
10 ns
CS
High to SDOUT HI-Z
t
27
10 ns
BUSY High in Master Serial Read After Convert
6
t
28
See Table 4 ns
CNVST
Low to SYNC Asserted Delay (All Modes)
t
29
383/500 ns
SYNC Deasserted to BUSY Low Delay t
30
13 ns
SLAVE SERIAL INTERFACE MODES (Refer to Figure 38 and Figure 39)
External SCLK Setup Time t
31
5 ns
External SCLK Active Edge to SDOUT Delay t
32
1 8 ns
SDIN Setup Time t
33
5 ns
SDIN Hold Time t
34
5 ns
External SCLK Period t
35
12.5 ns
External SCLK High t
36
5 ns
External SCLK Low t
37
5 ns
1
See the Conversion Control section.
2
All timings for wideband warp mode are the same as warp mode.
3
In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
4
See the Digital Interface section and the RESET section.
5
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
6
In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.