Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LQFP 48

18-Bit, 2 MSPS SAR ADC

AD7641

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Throughput

2 MSPS (wideband warp and warp mode)

1.5 MSPS (normal mode)

INL: ±2 LSB typical, ±3 LSB max; ±8 ppm of full scale

18-bit resolution with no missing codes

Dynamic range: 95.5 dB

SNR: 93.5 dB typical @ 20 kHz (V

REF

= 2.5 V)

THD: −112 dB typical @ 20 kHz (V

REF

= 2.5 V)

2.048 V internal reference: typ drift 10 ppm/°C; TEMP output

Differential input range: ±V

REF

up to 2.5 V)

No pipeline delay (SAR architecture)

Parallel (18-, 16-, or 8-bit bus) and

serial 5 V/3.3 V/2.5 V interface

SPI®/QSPI™/MICROWIRE™/DSP compatible

Single 2.5 V supply operation

Power dissipation

75 mW typical @ 2 MSPS with internal REF

2 μW in power-down mode

Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ

Speed upgrade of the

AD7674, AD7678, AD7679

APPLICATIONS

Medical instruments

High speed data acquisition/high dynamic data acquisition

Digital signal processing

Spectrum analysis

Instrumentation

Communications

ATE

GENERAL DESCRIPTION

The AD7641 is an 18-bit, 2 MSPS, charge redistribution SAR,

fully differential, analog-to-digital converter (ADC) that

operates from a single 2.5 V power supply. The part contains a

high speed, 18-bit sampling ADC, an internal conversion clock,

an internal reference (and buffer), error correction circuits, and

both serial and parallel system interface ports. It features two

very high sampling rate modes (wideband warp and warp) and

a fast mode (normal) for asynchronous rate applications. The

AD7641 is hardware factory calibrated and tested to ensure ac

parameters, such as signal-to-noise ratio (SNR), in addition to

the more traditional dc parameters of gain, offset, and linearity.

The AD7641 is available in Pb-free only packages with

operation specified from −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

04761-001

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

CLOCK

AD7641

DGNDD

AVDD

AGND

REF REFGND

IN+

IN–

RESET

CNVST

PDBUF

REFBUFIN

PDREF

REF

TEMP

D[17:0]

BUSY

D0/OB/2C

OGND

OVDD

MODE1

MODE0

REF AMP

NORMAL

SERIAL

PORT

PARALLEL

INTERFACE

SWITCHED

CAP DAC

WARP

Figure 1.

Table 1. PulSAR® Selection

Type/kSPS

100 to

250

500 to

570

650 to

1000

>1000

Pseudo

Differential

AD7651,

AD7660,

AD7661

AD7650,

AD7652,

AD7664,

AD7666

AD7653,

AD7667

True Bipolar

AD7610,

AD7663

AD7665

AD7612,

AD7671

True

Differential

AD7675 AD7676 AD7677

AD7621,

AD7622,

AD7623

18-Bit

Multichannel/

AD7631,

AD7678

AD7679

AD7634,

AD7674

AD7641,

AD7643

Simultaneous AD7654 AD7655

PRODUCT HIGHLIGHTS

1. Fast Throughput.

The AD7641 is a 2 MSPS, charge redistribution,

18-bit SAR ADC.

2. Superior Linearity.

The AD7641 has no missing 18-bit code.

3. Internal Reference.

The AD7641 has a 2.048 V internal reference with a typical

-chip TEMP sensor.

drift of ±10 ppm/°C and an on

Single-Supply Operation. 4.

2.5 V single supply.

ace

arrangement compatible with 2.5 V, 3.3 V, or 5 V logic.

The AD7641 operates from a

Serial or Parallel Interface.

Versatile parallel (16- or 8-bit bus) or 2-wire serial interf

Summary of content (28 pages)

PAGE 1
8-Bit, 2 MSPS SAR ADC AD7641 FEATURES APPLICATIONS Medical instruments High speed data acquisition/high dynamic data acquisition Digital signal processing Spectrum analysis Instrumentation Communications ATE GENERAL DESCRIPTION The AD7641 is an 18-bit, 2 MSPS, charge redistribution SAR, fully differential, analog-to-digital converter (ADC) that operates from a single 2.5 V power supply.
PAGE 2
AD7641 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs ............................................................................. 17 Applications....................................................................................... 1 Multiplexed Inputs ..................................................................... 17 General Description ....................................................................
PAGE 3
AD7641 SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 4
AD7641 Parameter Turn-On Settling Time REFBUFIN Output Voltage REFBUFIN Output Resistance EXTERNAL REFERENCE Voltage Range Current Drain REFERENCE BUFFER REFBUFIN Input Voltage Range REFBUFIN Input Current TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format 7 Pipeline Delay 8 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current 10 AVDD 11 DVDD OVDD12 Power Dissipation11 With Internal Referen
PAGE 5
AD7641 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
PAGE 6
AD7641 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK High Minimum Internal SCLK Low Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum BUSY High Width Maximum 500µA 0 0 0.5 8 14 2 3 1 0 0 0.630 0 1 3 16 26 6 7 5 0.5 0.5 0.870 1 0 3 32 52 15 16 5 10 9 1.350 1 1 3 64 103 31 32 5 28 26 2.
PAGE 7
AD7641 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs/Outputs IN+ 1 , IN−, REF, REFBUFIN, TEMP, INGND, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD OVDD AVDD to DVDD AVDD, DVDD to OVDD Digital Inputs PDREF, PDBUF 2 Internal Power Dissipation 3 Internal Power Dissipation 4 Junction Temperature Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 8
AD7641 REFGND REF IN– NC AGND IN+ AGND AVDD PDBUF PDREF REFBUFIN TEMP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 AVDD 2 35 AGND CNVST MODE0 3 MODE1 4 34 PD 33 D0/OB/2C 5 32 RESET CS 31 RD 30 29 DGND BUSY D2/A1 9 D3 10 28 D17 27 D16 D4/DIVSCLK[0] 11 D5/DIVSCLK[1] 12 26 D15 D14 AD7641 WARP 6 TOP VIEW (Not to Scale) NORMAL 7 D1/A0 8 25 04761-004 D13/RDERROR D11/SCLK D12/SYNC D10/SDOUT DVDD DGND OVDD D8/INVSCLK D9/RDC/SDIN OG
PAGE 9
AD7641 Pin No. 13 Mnemonic D6 or EXT/INT Type 1 DI/O 14 D7 or INVSYNC DI/O 15 D8 or INVSCLK DI/O 16 D9 or RDC DI/O or SDIN 17 18 OGND OVDD P P 19 20 21 DVDD DGND D10 or SDOUT P P DO 22 D11 or SCLK DI/O 23 D12 or SYNC DO 24 D13 or RDERROR DO Description When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus. When MODE[1:0] = 3, (serial mode), serial clock source select.
PAGE 10
AD7641 Pin No. 25 to 28 29 Mnemonic D[14:17] Type 1 DO BUSY DO 30 31 DGND RD P DI 32 CS DI 33 RESET DI 34 PD DI 35 CNVST DI 37 REF AI/O 38 39 40 43 45 46 REFGND IN− NC IN+ TEMP REFBUFIN AI AI AI AO AI/O 47 PDREF DI 48 PDBUF DI 1 Description Bit 14 to Bit 17 of the parallel port data output bus. These pins are always outputs, regardless of the interface mode. Busy Output.
PAGE 11
AD7641 TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.
PAGE 12
AD7641 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 2.0 2.5 1.5 2.0 1.5 1.0 0.5 DNL (LSB) INL (LSB) 1.0 0 –0.5 –1.0 –1.5 0.5 0 –0.5 –1.0 –2.0 65536 0 131072 196608 –2.0 262144 04761-008 –3.0 –1.5 04761-005 –2.5 0 65536 131072 CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 40000 30000 σ = 1.55 34844 35000 σ = 2.
PAGE 13
AD7641 –60 –80 –100 –120 –140 100 200 300 400 500 600 700 800 900 04761-014 500 600 85 14.0 83 13.6 81 13.2 79 12.8 77 12.4 10 100 SNR, SINAD (dB) 14.4 ENOB (Bits) 87 12.
PAGE 14
AD7641 100000 AVDD 10000 OPERATING CURRENTS (µA) 95.0 SNR 94.5 SINAD 94.0 1000 93.5 93.0 –60 –50 –40 –30 –20 OVDD = 2.5V, ALL MODES 10 1 OVDD = 3.3V, ALL MODES 0.1 0.01 10 0 –10 DVDD 100 PDREF = PDBUF = HIGH 100 1k INPUT LEVEL (dB) 10k 100k 1M 10M SAMPLING RATE (SPS) Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 19. Operating Current vs. Sample Rate 16 20 14 18 12 16 OVDD = 2.5V @ 85°C t12 DELAY (ns) OVDD = 2.5V @ 25°C 10 DVDD 8 OVDD, 3.
PAGE 15
AD7641 APPPLICATIONS INFORMATION IN+ AGND LSB MSB 131,072C 65,536C 4C 2C C SW+ SWITCHES CONTROL C BUSY REF COMP REFGND 4C 2C C OUTPUT CODE C MSB SW– LSB CNVST AGND IN– 04761-021 131,072C 65,536C CONTROL LOGIC Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7641 is a very fast, low power, single-supply, precise 18-bit ADC using successive approximation architecture. The AD7641 features different modes to optimize performances according to the applications.
PAGE 16
AD7641 TRANSFER FUNCTIONS Table 8. Output Codes and Ideal Input Voltages Description FSR −1 LSB FSR − 2 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 111...111 111...110 111...101 1 2 000...010 000...001 000...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB Digital Output Code (Hex) Straight Twos Binary Complement 1 0x3FFFF 0x1FFFF1 0x3FFFE 0x1FFFE 0x20001 0x00001 0x20000 0x00000 0x1FFFF 0x3FFFF 0x30001 0x20001 0x30000 2 0x200002 Analog Input VREF = 2.048 V +2.0479844 V +2.0479688 V +15.
PAGE 17
AD7641 TYPICAL CONNECTION DIAGRAM Figure 23 shows a typical connection diagram for the AD7641. Different circuitry shown in this diagram is optional and is discussed in the following sections. ANALOG INPUTS Figure 24 shows an equivalent circuit of the input structure of the AD7641. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.
PAGE 18
AD7641 Single-to-Differential Driver The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7641. The noise coming from the driver is filtered by the AD7641 analog input circuit 1-pole, low-pass filter made by RIN and CIN or by the external filter, if one is used.
PAGE 19
AD7641 External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) To use an external reference along with the internal buffer, PDREF should be high and PDBUF should be low. This powers down the internal reference and allows the 1.2 V reference to be applied to REFBUFIN, producing 2.048 V (typically) on the REF pin. External 2.5 V Reference (PDBUF = High, PDREF = High) To use an external 2.5 V reference directly on the REF pin, PDREF and PDBUF should both be high.
PAGE 20
AD7641 POWER SUPPLY The AD7641 uses three sets of power supply pins: an analog 2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.3 V and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 23.
PAGE 21
AD7641 INTERFACES DIGITAL INTERFACE PARALLEL INTERFACE The AD7641 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The serial interface is multiplexed on the parallel data bus. The AD7641 digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic high output voltage. In most applications, the OVDD supply pin of the AD7641 is connected to the host system interface 2.5 V or 3.
PAGE 22
AD7641 CS = 0 SERIAL INTERFACE t1 CNVST, RD BUSY The AD7641 is configured to use the serial interface when MODE[1:0] = 3. The AD7641 outputs 18 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 18 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock. t4 t3 DATA BUS MASTER SERIAL INTERFACE Internal Clock t12 045761-034 PREVIOUS CONVERSION t13 Figure 33.
PAGE 23
AD7641 EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 DIVSCLK[1:0] = 0 CS, RD t3 CNVST t28 BUSY t30 t29 t25 SYNC t18 t19 t14 t20 1 SCLK t24 t21 2 3 16 17 t26 18 t15 t27 D17 X t16 D16 D2 D1 D0 04761-036 SDOUT t23 t22 Figure 35.
PAGE 24
AD7641 SLAVE SERIAL INTERFACE The AD7641 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or a discontinuous clock.
PAGE 25
AD7641 RD = 0 INVSCLK = 0 EXT/INT = 1 CS BUSY t35 t36 t37 SCLK 1 2 t31 3 16 17 18 19 20 t32 X SDOUT D17 t16 D16 D15 D1 D0 X17 X16 X16 X15 X1 X0 Y17 Y16 SDIN X17 t33 04761-039 t34 Figure 38. Slave Serial Data Timing for Reading (Read After Convert) t31 EXT/INT = 1 RD = 0 INVSCLK = 0 CS t3 CNVST t35 BUSY t36 SCLK t37 2 1 4 3 16 17 18 SDOUT X D17 D16 D15 D2 D1 D0 t16 Figure 39.
PAGE 26
AD7641 MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) The AD7641 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD7641 is designed to interface with a parallel 8-bit or 16-bit wide interface or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7641 to prevent digital noise from coupling into the ADC.
PAGE 27
AD7641 APPLICATION HINTS LAYOUT While the AD7641 has very good immunity to noise on the power supplies, exercise care with the grounding layout. To facilitate the use of ground planes that can be easily separated, design the printed circuit board that houses the AD7641 so that the analog and digital sections are separated and confined to certain areas of the board. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7641, or as close as possible to the AD7641.
PAGE 28
AD7641 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 PIN 1 7.00 BSC SQ TOP VIEW 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY SEATING PLANE (PINS DOWN) 25 12 13 24 0.27 0.22 0.17 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 41. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 7.00 BSC SQ 0.60 MAX 0.