Datasheet

Data Sheet AD7634
Rev. B | Page 5 of 32
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V
REF
= 5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (See Figure 35 and Figure 36)
Convert Pulse Width t
1
10 ns
Time Between Conversions t
2
Warp Mode/Normal Mode/Impulse Mode
1
1.49/1.75/2.22 s
CNVST Low to BUSY High Delay
t
3
35 ns
BUSY High All Modes (Except Master Serial Read After Convert) t
4
Warp Mode/Normal Mode/Impulse Mode
1.18/1.43/1.68
s
Aperture Delay t
5
2 ns
End of Conversion to BUSY Low Delay t
6
10 ns
Conversion Time t
7
Warp Mode/Normal Mode/Impulse Mode
1.18/1.43/1.68
s
Acquisition Time, All modes t
8
310 ns
RESET Pulse Width t
9
10 ns
PARALLEL INTERFACE MODES (See Figure 37 and Figure 39)
CNVST Low to Data Valid Delay
t
10
Warp Mode/Normal Mode/Impulse Mode
1.15/1.40/1.65
s
Data Valid to BUSY Low Delay t
11
20 ns
Bus Access Request to Data Valid t
12
40 ns
Bus Relinquish Time t
13
2 15 ns
MASTER SERIAL INTERFACE MODES
2
(See Figure 41 and Figure 42)
CS Low to SYNC Valid Delay
t
14
10 ns
CS Low to Internal SDCLK Valid Delay
2
t
15
10 ns
CS Low to SDOUT Delay
t
16
10 ns
CNVST Low to SYNC Delay, Read During Convert
t
17
Warp Mode/Normal Mode/Impulse Mode
50/290/530
ns
SYNC Asserted to SDCLK First Edge Delay t
18
3 ns
Internal SDCLK Period
3
t
19
30 45 ns
Internal SDCLK High
3
t
20
15 ns
Internal SDCLK Low
3
t
21
10 ns
SDOUT Valid Setup Time
3
t
22
4 ns
SDOUT Valid Hold Time
3
t
23
5 ns
SDCLK Last Edge to SYNC Delay
3
t
24
5 ns
CS High to SYNC High-Z
t
25
10 ns
CS High to Internal SDCLK High-Z
t
26
10 ns
CS High to SDOUT High-Z
t
27
10 ns
BUSY High in Master Serial Read After Convert
3
t
28
See Table 4
CNVST Low to SYNC Delay Read After Convert
Warp Mode/Normal Mode/Impulse Mode t
29
1.1/1.3/1.5
s
SYNC Deasserted to BUSY Low Delay t
30
25 ns