Datasheet

AD7634 Data Sheet
Rev. B | Page 28 of 32
External Clock Data Read After/During Conversion
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion is initiated.
This method allows the full throughput and the use of a slower
SDCLK frequency. Again, it is recommended to use a
discontinuous SDCLK whenever possible to minimize potential
incorrect bit decisions. For the different modes, the use of a slower
SDCLK, such as 20 MHz in warp mode, 15 MHz in normal mode,
and 13 MHz in impulse mode, can be used.
SDIN
SDOUT
D0
123 1718
BUSY
EXT/INT = 1 INVSCLK = 0
CS
SDCLK
4
D2
D1
19 20
MODE[1:0] = 3 RD = 0
16
D17
D16
D15
X17 X16
21
X0
X2
X1
X17
X16
X15
Y17 Y16
t
31
t
31
X*
t
32
t
16
t
33
t
34
t
37
t
35
t
36
*A DISCONTINUOUS SDCLK IS RECOMMENDED.
0
6406-042
Figure 44. Slave Serial Data Timing for Reading (Read After Convert)
SDOUT
D0
123
BUSY
EXT/INT = 1 INVSCLK = 0
CS
SDCLK
17
D1
MODE[1:0] = 3 RD = 0
18
D17
D16
t
31
t
31
t
32
t
16
t
37
t
35
t
36
CNVST
X*
X*
X* X*
X*
X*
t
27
*A DISCONTINUOUS SDCLK IS RECOMMENDED.
DATA = SDIN
06406-043
Figure 45. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)