Datasheet
Data Sheet AD7634
Rev. B | Page 23 of 32
capacitor with the 100 nF capacitor placed as close as possible
to the AD7634.
Power Sequencing
The AD7634 requires sequencing of the AVDD and DVDD
supplies. AVDD should come up prior to or simultaneously
with DVDD. This can be achieved using the configuration in
Figure 27 or sequencing the supplies in that manner. The
other supplies can be sequenced as desired as long as absolute
maximum ratings are observed. The AD7634 is very insensitive
to power supply variations on AVDD over a wide frequency
range, as shown in Figure 33.
30
35
40
45
50
55
60
65
70
75
1 10 100 1000 10000
0
6406-051
FREQUENCY (kHz)
PSRR (dB)
Figure 33. AVDD PSRR vs. Frequency
Power Dissipation vs. Throughput
In impulse mode, the AD7634 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which allows
a significant power savings when the conversion rate is reduced
(see Figure 34). This feature makes the AD7634 ideal for very
low power, battery-operated applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital supply
currents even further, drive the digital inputs close to the power
rails, that is, OVDD and OGND.
1000
1
1 1000000100000
SAMPLING RATE (kSPS)
POWER DISSIPATION (mW)
10010 100001000
10
100
06406-048
IMPULSE MODE POWER
WARP MODE POWER
PDREF = PDBUF = HIGH
Figure 34. Power Dissipation vs. Sample Rate
Power Down
Setting PD = high powers down the AD7634, thus reducing
supply currents to their minimums, as shown in Figure 23.
When the ADC is in power down, the current conversion
(if any) is completed and the digital bus remains active. To
further reduce the digital supply currents, drive the inputs to
OVDD or OGND.
Power down can also be programmed with the configuration
register. See the Software Configuration section for details. Note
that when using the configuration register, the PD input is a don’t
care and should be tied to either high or low.
CONVERSION CONTROL
The AD7634 is controlled by the
CNVST
input. A falling edge
on
CNVST
is all that is necessary to initiate a conversion. A
detailed timing diagram of the conversion process is shown in
Figure 35. Once initiated, it cannot be restarted or aborted, even
by the power-down input, PD, until the conversion is complete.
The
CNVST
signal operates independently of
CS
and
RD
signals.
BUSY
MODE
CONVERT ACQUIREACQUIRE CONVERT
CNVST
t
1
t
2
t
4
t
3
t
5
t
6
t
7
t
8
0
6406-033
Figure 35. Basic Conversion Timing
Although
CNVST
is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot, undershoot, or ringing.
The
CNVST
trace should be shielded with ground and a low value
(such as 50 Ω) serial resistor termination should be added close
to the output of the component that drives this line.
For applications where SNR is critical, the
CNVST
signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for
CNVST
generation, or by clocking
CNVST
with a
high frequency, low jitter clock, as shown in Figure 27.