Datasheet

AD7631 Data Sheet
Rev. B | Page 6 of 32
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SDCLK First Edge Delay Minimum t
18
3 20 20 20 ns
Internal SDCLK Period Minimum t
19
30 60 120 240 ns
Internal SDCLK Period Maximum t
19
45 90 180 360 ns
Internal SDCLK High Minimum t
20
15 30 60 120 ns
Internal SDCLK Low Minimum t
21
10 25 55 115 ns
SDOUT Valid Setup Time Minimum t
22
4 20 20 20 ns
SDOUT Valid Hold Time Minimum t
23
5 8 35 90 ns
SDCLK Last Edge to SYNC Delay Minimum t
24
5 7 35 90 ns
BUSY High Width Maximum t
28
2.55 3.40 5.00 8.20 µs
NOTES
1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK,
AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
1.6mA I
OL
500µA I
OH
1.4V
TO OUTPUT
PIN
C
L
60pF
0
6588-002
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SDCLK Outputs, C
L
= 10 pF
0.8V
2V
2V
0.8V0.8V
2V
t
DELAY
t
DELAY
06588-003
Figure 3. Voltage Reference Levels for Timing