Datasheet

Data Sheet AD7631
Rev. B | Page 5 of 32
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V
REF
= 5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (See Figure 35 and Figure 36)
Convert Pulse Width t
1
10 ns
Time Between Conversions t
2
4.0 µs
CNVST Low to BUSY High Delay
t
3
35 ns
BUSY High All Modes (Except Master Serial Read After Convert) t
4
1.68
µs
Aperture Delay t
5
2 ns
End of Conversion to BUSY Low Delay t
6
10 ns
Conversion Time t
7
1.68
µs
Acquisition Time t
8
2.32 ns
RESET Pulse Width t
9
10 ns
PARALLEL INTERFACE MODES (See Figure 37 and Figure 39)
CNVST Low to DATA Valid Delay
t
10
1.65
µs
DATA Valid to BUSY Low Delay t
11
20 ns
Bus Access Request to DATA Valid t
12
40 ns
Bus Relinquish Time t
13
2 15 ns
MASTER SERIAL INTERFACE MODES
1
(See Figure 41 and Figure 42)
CS Low to SYNC Valid Delay
t
14
10 ns
CS Low to Internal SDCLK Valid Delay
1
t
15
10 ns
CS Low to SDOUT Delay
t
16
10 ns
CNVST Low to SYNC Delay, Read During Convert
t
17
530 ns
SYNC Asserted to SDCLK First Edge Delay t
18
3 ns
Internal SDCLK Period
2
t
19
30 45 ns
Internal SDCLK High
2
t
20
15 ns
Internal SDCLK Low
2
t
21
10 ns
SDOUT Valid Setup Time
2
t
22
4 ns
SDOUT Valid Hold Time
2
t
23
5 ns
SDCLK Last Edge to SYNC Delay
2
t
24
5 ns
CS High to SYNC HIGH-Z
t
25
10 ns
CS High to Internal SDCLK HIGH-Z
t
26
10 ns
CS High to SDOUT HIGH-Z
t
27
10 ns
BUSY High in Master Serial Read After Convert
2
t
28
See Table 4
CNVST Low to SYNC Delay, Read After Convert
t
29
1.5
µs
SYNC Deasserted to BUSY Low Delay t
30
25 ns
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES
1
(See Figure 44, Figure 45, and Figure 47)
External SDCLK, SCCLK Setup Time t
31
5 ns
External SDCLK Active Edge to SDOUT Delay t
32
2 18 ns
SDIN/SCIN Setup Time t
33
5 ns
SDIN/SCIN Hold Time t
34
5 ns
External SDCLK/SCCLK Period t
35
25 ns
External SDCLK/SCCLK High t
36
10 ns
External SDCLK/SCCLK Low t
37
10 ns
1
In serial interface modes, the SYNC, SDSCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
In serial master read during convert mode. See Table 4 for serial master read after convert mode.