Datasheet

Data Sheet AD7631
Rev. B | Page 29 of 32
HARDWARE CONFIGURATION
The AD7631 can be configured at any time with the dedicated
hardware pins BIPOLAR, TEN, D0/OB/
2C
, and PD for parallel
mode (MODE[1:0] = 0, 1, or 2) or serial hardware mode
(MODE[1:0] = 3, HW/
SW
= high). Programming the AD7631
for mode selection and input range configuration can be done
before or during conversion. Like the RESET input, the ADC
requires at least one acquisition time to settle, as indicated in
Figure 46. See Table 6 for pin descriptions. Note that these
inputs are high impedance when using the software
configuration mode.
SOFTWARE CONFIGURATION
The pins multiplexed on D[17:14] used for software
configuration are: HW/
SW
, SCIN, SCCLK, and
SCCS
. The
AD7631 is programmed using the dedicated write-only
serial configurable port (SCP) for conversion mode, input range
selection, output coding, and power-down using the serial
configuration register. See Table 11 for details of each bit in the
configuration register. The SCP can only be used in serial software
mode selected with MODE[1:0] = 3 and HW/
SW
= low because
the port is multiplexed on the parallel interface.
The SCP is accessed by asserting the port’s chip select,
SCCS
,
and then writing SCIN synchronized with SCCLK, which (like
SDCLK) is edge sensitive depending on the state of INVSCLK.
See Figure 47 for timing details. SCIN is clocked into the
configuration register MSB first. The configuration register is
an internal shift register that begins with Bit 8, the START bit.
The 9
th
SCCLK edge updates the register and allows the new
settings to be used. As indicated in the timing diagram, at least one
acquisition time is required from the 9
th
SCCLK edge. Bits [1:0] are
reserved bits and are not written to while the SCP is being updated.
The SCP can be written to at any time, up to 40 MHz, and it is
recommended to write to while the AD7631 is not busy
converting, as detailed in Figure 47. In this mode, the full
670 kSPS is not attainable because the time required for SCP
access is (t
31
+ 9 × 1/SCCLK + t
8
) minimum. If the full
throughput is required, the SCP can be written to during
conversion; however, it is not recommended to write to the SCP
during the last 600 ns of conversion (BUSY = high) or performance
degradation can result. In addition, the SCP can be accessed in
both serial master and serial slave read during and read after
convert modes.
Note that at power-up, the configuration register is undefined.
The RESET input clears the configuration register (sets all bits
to 0), therefore placing the configuration to 0 V to 5 V input,
normal mode, and twos complemented output.
Table 11. Configuration Register Description
Bit Mnemonic Description
8 START
START bit. With the SCP enabled (
SCCS
= low),
when START is high, the first rising edge of
SCCLK (INVSCLK = low) begins to load the
register with the new configuration.
7 BIPOLAR Input Range Select. Used in conjunction with
Bit 6, TEN, per the following.
Input Range (V) BIPOLAR TEN
0 to 5 Low Low
0 to 10 Low High
±5 High Low
±10 High High
6 TEN Input Range Select. See Bit 7, BIPOLAR.
5 PD Power Down.
PD = low, normal operation.
PD = high, power down the ADC. The SCP is
accessible while in power down. To power up
the ADC, write PD = low on the next
configuration setting.
4 RSV Reserved.
3 RSV Reserved.
2
OB/
2C
Output coding.
OB/
2C
= low, use twos complement output.
OB/
2C
= high, use straight binary output.
1 RSV Reserved.
0 RSV Reserved.
D0/OB/2C,
PD
BUSY
HW/SW = 1
CNVST
BIPOLAR,
TEN
t
8
PD = 0
t
8
0
6588-046
Figure 46. Hardware Configuration Timing