Datasheet

AD7631 Data Sheet
Rev. B | Page 26 of 32
EXT/INT = 0
RDC/SDIN = 1 INVSCLK = INVSYNC = 0
D17 D16 D2 D1 D0X
123 161718
BUSY
SYNC
SDCLK
SDOUT
CNVST
CS, RD
t
23
t
18
t
15
t
14
t
17
t
3
t
22
t
16
t
1
t
25
t
26
t
24
t
27
t
19
t
20
t
21
MODE[1:0] = 3
06588-041
Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
BUSY
SYNC
SDCLK
SDOUT
123 161718
D17 D16 D2 D1 D0
X
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
CNVST
CS, RD
EXT/INT = 0
t
23
t
22
t
16
t
15
t
14
t
29
t
19
t
21
t
20
t
18
t
28
t
30
t
24
t
25
t
26
t
27
t
3
MODE[1:0] = 3
06588-042
Figure 42. Master Serial Data Timing for Reading (Read After Convert)
SLAVE SERIAL INTERFACE
The pins multiplexed on D[13:6] used for slave serial
interface are: EXT/
INT
, INVSCLK, SDIN, SDOUT, SDCLK,
and RDERROR.
External Clock (MODE[1:0] = 3, EXT/
INT
= High)
Setting the EXT/
INT
= high allows the AD7631 to accept an
externally supplied serial data clock on the SDCLK pin. In this
mode, several methods can be used to read the data. The external
serial clock is gated by
CS
. When
CS
and
RD
are both low, the
data can be read after each conversion or during the following
conversion. A clock can be either normally high or normally
low when inactive. For detailed timing diagrams, see Figure 44
and Figure 45.
While the AD7631 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins,
or degradation of the conversion result may occur. This is
particularly important during the last 550 ns of the conversion
phase because the AD7631 provides error correction circuitry
that can correct for an improper bit decision made during
the first part of the conversion phase. For this reason, it is
recommended that any external clock provided is a
discontinuous clock that transitions only when BUSY is low,
or, more importantly, that it does not transition during the
last 450 ns of BUSY high.