Datasheet

AD7626 Data Sheet
Rev. B | Page 6 of 28
TIMING DIAGRAMS
CLK+
t
CYC
1615
CNV+
116152 123
t
CNVH
t
CLKL
DCO+
1615 1 16152
1
23
D+
SAMPLE N S
A
MPLE N + 1
D–
D15
N
D14
N
D1
N
CLK–
CNV–
DCO–
D0
N – 1
ACQUISITION
ACQUISITION ACQUISITION
t
DCO
t
D
t
CLK
0
t
MSB
D1
N – 1
D15
N + 1
D14
N + 1
D0
N
0
D13
N + 1
t
CLKD
0
7648-003
Figure 2. Echoed-Clock Interface Mode Timing Diagram
CLK+
1817 1 42
1
23
t
CLKL
D+
D–
CLK–
D0
N – 1
D1
N – 1
ACQUISITION
ACQUISITION
ACQUISITION
t
CLKD
t
CLK
t
MSB
18173
D15
N
D14
N
D1
N
00 1
D0
N
D15
N + 1
00 1
t
CYC
C
NV+
t
CNVH
SAMPLE N
S
A
MPLE N + 1
CNV–
07648-004
Figure 3. Self-Clocked Interface Mode Timing Diagram