Datasheet

Data Sheet AD7626
Rev. B | Page 5 of 28
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
Time Between Conversions
1
t
CYC
100 10,000 ns
CNV High Time t
CNVH
10 40 ns
CNV to D (MSB) Ready t
MSB
100 ns
CNV to Last CLK (LSB) Delay t
CLKL
72 ns
CLK Period
2
t
CLK
3.33 4 (t
CYC
− t
MSB
+ t
CLKL
)/n ns
CLK Frequency f
CLK
250 300 MHz
CLK to DCO Delay (Echoed-Clock Mode) t
DCO
0 4 7 ns
DCO to D Delay (Echoed-Clock Mode) t
D
0 1 ns
CLK to D Delay t
CLKD
0 4 7 ns
1
The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of t
CYC
, the subsequent conversion result is invalid.
2
For the maximum CLK period, the window available to read data is t
CYC
− t
MSB
+ t
CLKL
. Divide this time by the number of bits (n) to be read giving the maximum CLK±
frequency that can be used for a given conversion CNV frequency. In echoed-clock interface mode, n = 16; in self-clocked interface mode, n = 18.