Datasheet

Data Sheet AD7626
Rev. B | Page 17 of 28
TYPICAL CONNECTION DIAGRAM
07648-027
AD7626
C
REF
10µF
1, 2
V+
ADR434
8
ADR444
CONVERSION
4
CONTROL
CMOS (CNV+ ONLY)
OR
LVDS CNV+ AND CNV–
USING 100Ω
TERMINATION RESISTOR
DIGITAL INTERFACE SIGNALS
DIGITAL HOST
LVDS TRANSMIT AND RECEIVE
VDD1
VDD2
CAP1
REFIN
EN0
EN1
VDD2
CNV–
24
23
22
21
20
19
18
CNV+ D– D+ VIO GND DCO– DCO+ CLK–
GND
IN+
IN–
VCM
VDD1
VDD1
VDD2
CLK+
REF
GND
REF REF
CAP2
GND
CAP2 CAP2
10nF
100nF
100nF
10 µ F
ADR280
8
VIO
10kΩ
3
10kΩ
CONTROL FOR
ENABLE
PINS
VIO
(2.5V)
5
100Ω 100Ω
PADDLE
CAPACITOR ON OUTPUT
FOR STABILITY
10µF
1
100nF
100nF
FERRITE
BEAD
6
VDD1
(5V)
VDD2
(2.5V)
VDD1
(5V)
VDD2
(2.5V)
100nF
VDD2
(2.5V)
IN+
IN–
VCM
SEE THE DRIVING
THE AD7625 SECTION
7
8 9 10 11 12 13 14 15 16 17
100Ω
100Ω
1
2
3
4
5
6
7
32 31 30 29 28 27 26 25
1
SEE THE LAYOUT, DECOUPLING, AND GROUNDING SECTION.
2
C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESR AND ESL.
3
USE PULL-UP OR PULL-DOWN RESISTORS TO CONTROL EN0 AND EN1 DURING POWER-UP. EN0 AND EN1 INPUTS CAN BE
FIXED IN HARDWARE OR CONTROLLED USING A DIGITAL HOST (EN0 = 0 AND EN1 = 0 PUTS THE ADC IN POWER-DOWN).
4
OPTION TO USE A CMOS (CNV+) OR LVDS (CNV±) INPUT TO CONTROL CONVERSIONS.
5
TO ENABLE SELF-CLOCKED MODE, TIE DCO+ TO GND.
6
CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE THE TRACE TO PIN 19 AND PIN 20 FROM THE TRACE TO PIN 1 USING A
FERRITE BEAD SIMILAR TO WURTH 74279266.
7
SEE THE DRIVING THE AD7626 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS.
8
SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS.
Figure 31. Typical Application Diagram