Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LFCSP-32-VQ

16-Bit, 6 MSPS, PulSAR

Differential ADC

Data Sheet

AD7625

Rev. A

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FEATURES

Throughput: 6 MSPS

SNR: 93 dB

INL: ±0.45 LSB typical, ±1 LSB maximum

DNL: ±0.3 LSB typical, ±0.5 LSB maximum

Power dissipation: 135 mW

32-lead LFCSP (5 mm × 5 mm)

SAR architecture

No latency/no pipeline delay

16-bit resolution with no missing codes

Zero error: ±1.5 LSB

Differential input voltage: ±4.096 V

Serial LVDS interface

Self-clocked mode

Echoed-clock mode

Can use LVDS or CMOS for conversion control (CNV signal)

Reference options

Internal: 4.096 V

External (1.2 V) buffered to 4.096 V

External: 4.096 V

APPLICATIONS

High dynamic range telecommunications

Receivers

Digital imaging systems

High speed data acquisition

Spectrum analysis

Test equipment

FUNCTIONAL BLOCK DIAGRAM

AD7625

CLOCK

LOGIC

SERIAL

LVDS

IN–

IN+

REFIN REF VCM

SAR

÷2

CNV+, CNV–

VIO

D+, D–

DCO+, DCO–

CLK+, CLK–

1.2V

BAND GAP

CAP

DAC

07652-001

Figure 1.

GENERAL DESCRIPTION

The AD7625 is a 16-bit, 6 MSPS, charge redistribution successive

approximation register (SAR) based architecture analog-to-digital

converter (ADC). SAR architecture allows unmatched perfor-

mance both in noise (93 dB SNR) and in linearity (1 LSB). The

AD7625 contains a high speed, 16-bit sampling ADC, an internal

conversion clock, and an internal buffered reference. On the

CNV± rising edge, it samples the voltage difference between the

IN+ and IN− pins. The voltages on these pins swing in opposite

phase between 0 V and REF. The 4.096 V reference voltage, REF,

can be generated internally or applied externally.

All converted results are available on a single LVDS self-clocked

or echoed-clock serial interface, reducing external hardware

connections.

The AD7625 is housed in a 32-lead, 5 mm × 5 mm LFCSP with

operation specified from −40°C to +85°C.

Table 1. Fast PulSAR® ADC Selection

Input Type

Resolution (Bits)

1 MSPS to <2 MSPS

2 MSPS to 3 MSPS

6 MSPS

Differential (Ground Sense) 16 AD7653

16 AD7667

16 AD7980

16 AD7983

True Bipolar 16 AD7671

Differential (Antiphase) 16 AD7677 AD7621 AD7625

16 AD7623 AD7622

18 AD7643 AD7641

18 AD7982

18 AD7984

Summary of content (24 pages)

PAGE 1
6-Bit, 6 MSPS, PulSAR Differential ADC AD7625 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS High dynamic range telecommunications Receivers Digital imaging systems High speed data acquisition Spectrum analysis Test equipment REFIN REF VCM 1.2V BAND GAP IN+ VIO CLOCK ÷2 LOGIC CAP DAC IN– CNV+, CNV– D+, D– SAR AD7625 SERIAL LVDS DCO+, DCO– CLK+, CLK– 07652-001 Throughput: 6 MSPS SNR: 93 dB INL: ±0.45 LSB typical, ±1 LSB maximum DNL: ±0.3 LSB typical, ±0.
PAGE 2
AD7625 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Information .................................................................... 13 Applications ....................................................................................... 1 Converter Information .............................................................. 13 Functional Block Diagram ........................................................
PAGE 3
Data Sheet AD7625 SPECIFICATIONS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 4
AD7625 Parameter LVDS I/O (ANSI-644) Data Format Differential Output Voltage, VOD Common-Mode Output Voltage, VOCM 2 Differential Input Voltage, VID Common-Mode Input Voltage, VICM POWER SUPPLIES Specified Performance VDD1 VDD2 VIO Operating Currents Static—Not Converting VDD1 VDD2 VIO With Internal Reference VDD1 VDD2 VIO Without Internal Reference VDD1 VDD2 VIO Power Dissipation 3 Static—Not Converting With Internal Reference Without Internal Reference Energy per Conversion TEMPERATURE RANGE Specified Per
PAGE 5
Data Sheet AD7625 TIMING SPECIFICATIONS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
PAGE 6
AD7625 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Analog Inputs/Outputs IN+, IN− to GND1 2 REF to GND VCM, CAP2 to GND CAP1, REFIN to GND Supply Voltage VDD1 VDD2, VIO Digital Inputs to GND Digital Outputs to GND Input Current to Any Pin Except Supplies3 Operating Temperature Range (Commercial) Storage Temperature Range Junction Temperature ESD θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
PAGE 7
Data Sheet AD7625 32 31 30 29 28 27 26 25 REF GND REF REF CAP2 GND CAP2 CAP2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD7625 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 GND IN+ IN– VCM VDD1 VDD1 VDD2 CLK+ NOTES 1. CONNECT THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS. 07652-002 CNV+ D– D+ VIO GND DCO– DCO+ CLK– 9 10 11 12 13 14 15 16 VDD1 VDD2 CAP1 REFIN EN0 EN1 VDD2 CNV– Figure 2. Table 6. Pin Function Descriptions Pin No.
PAGE 8
AD7625 Data Sheet Pin No. 25, 26, 28 Mnemonic CAP2 Type 1 AO 27 29, 30, 32 GND REF P AI/O 31 EP GND Exposed Pad P 1 Description Connect all three CAP2 pins together and decouple them with the shortest trace possible to a single 10 μF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 27 (GND). Ground. Return path for the 10 μF capacitor connected to Pin 25, Pin 26, and Pin 28. Buffered Reference Voltage. When using the internal reference or the 1.
PAGE 9
Data Sheet AD7625 0 –20 –20 –40 –40 –60 –60 –80 –100 –120 –100 –120 –140 –160 –160 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (MHz) –180 0 10 15 20 25 30 35 40 45 Figure 6. FFT 2 kHz Input Tone, Zoom In on Input Tone and Harmonics 0 INPUT TONE = 50kHz SNR = 93.04dB SINAD = 92.63dB THD = –103.57dB SFDR = –102.69dB –40 –40 AMPLITUDE (dB) –60 –80 –100 –120 –60 –80 –100 –120 –140 –140 –160 –160 0 0.5 1.0 1.5 2.0 2.5 3.
PAGE 10
AD7625 Data Sheet –94 –100.5 –96 –0.5dBFS –101.0 –98 –100 INTERNAL REF –3dBFS THD (dB) THD (dB) –101.5 –1dBFS –102 –104 –106 –102.0 –10dBFS –108 –102.5 EXTERNAL REF –110 –5dBFS –112 –103.0 0 20 40 60 80 100 120 INPUT FREQUENCY (kHz) –103.5 –60 07652-012 –116 0 20 40 60 80 100 120 Figure 12. THD vs. Temperature (−0.5 dB, 20 kHz Input Tone) 93.2 93.8 93.0 93.6 DYNR vs. TEMP INTERNAL REF DYNR vs. TEMP EXTERNAL REF 93.4 92.8 SINAD vs. TEMP EXTERNAL REF SINAD (dB) 93.
PAGE 11
Data Sheet AD7625 140,000 250,000 262,144 SAMPLES STD DEVIATION = 0.4829 128,084 129,601 262,144 SAMPLES STD DEVIATION = 0.5329 FEC8 FEC9 120,000 201,320 200,000 100,000 COUNT COUNT 150,000 100,000 80,000 60,000 40,000 50,000 0 FEC7 54 FEC8 20,000 46 FEC9 FECA FECB FECC 0 FECD CODE (HEX) 07652-022 0 30,073 Figure 15. Histogram of 262,144 Conversions of a DC Input at the Code Center (Internal Reference) 262,144 SAMPLES STD DEVIATION = 0.
PAGE 12
AD7625 Data Sheet TERMINOLOGY Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of an 80 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN− at frequency fS. CMRR (dB) = 10log(Pf/PfS) Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter.
PAGE 13
Data Sheet AD7625 THEORY OF OPERATION IN+ GND LSB MSB 32,768C 16,384C 4C 2C SWITCHES CONTROL SW+ C C REF (4.096V) CLK+, CLK– COMP GND 4C 2C C DATA TRANSFER D+, D– OUTPUT CODE C MSB DCO+, DCO– SW– LSB CNV+, CNV– GND CONVERSION CONTROL IN– LVDS INTERFACE 07652-030 32,768C 16,384C CONTROL LOGIC Figure 18.
PAGE 14
AD7625 Data Sheet TRANSFER FUNCTIONS ANALOG INPUTS The AD7625 uses a 4.096 V reference. The AD7625 converts the differential voltage of the antiphase analog inputs (IN+ and IN−) into a digital output. The analog inputs, IN+ and IN−, require a 2.048 V common-mode voltage (REF/2). The analog inputs, IN+ and IN−, applied to the AD7625 must be 180° out of phase with each other. Figure 20 shows an equivalent circuit of the input structure of the AD7625.
PAGE 15
Data Sheet AD7625 TYPICAL CONNECTION DIAGRAM V+ ADR434 8 ADR444 CAPACITOR ON OUTPUT FOR STABILITY CREF 10µF1, 2 VDD1 (5V) 10µF1 10nF 1 VDD1 2 VDD2 ADR280 8 10µF VIO 10kΩ 3 3 CAP1 4 REFIN 32 31 30 29 28 27 26 25 GND REF REF CAP2 GND CAP2 CAP2 100nF REF 100nF VDD2 (2.
PAGE 16
AD7625 Data Sheet DRIVING THE AD7625 ADA4899-1 Differential Analog Input Source U1 ANALOG INPUT (UNIPOLAR 0V TO 4.096V) Figure 24 shows an ADA4899-1 driving each differential input to the AD7625. Single-Ended-to-Differential Driver 590Ω For applications using unipolar analog signals, a single-endedto-differential driver, as shown in Figure 23, allows for a differential input into the part. This configuration, when provided with an input signal of 0 V to 4.096 V, produces a differential ±4.
PAGE 17
Data Sheet AD7625 VOLTAGE REFERENCE OPTIONS Table 8. Voltage Reference Options 1 The AD7625 allows flexible options for creating and buffering the reference voltage. The AD7625 conversions refer to 4.096 V only. The various options creating this 4.096 V reference are controlled by the EN1 and EN0 pins (see Table 8). Option A EN1 1 EN0 1 B 0 1 C 1 0 1 A V+ V+ EN1 = 0 and EN0 = 0 is an illegal state. SETTING EN1 = 1 AND EN0 = 1 ENABLES THE INTERNAL REFERENCE AND REFERENCE BUFFER.
PAGE 18
AD7625 Data Sheet The AD7625 uses both 5 V (VDD1) and 2.5 V (VDD2) power supplies, as well as a digital input/output interface supply (VIO). VIO allows a direct interface with 2.5 V logic only. VIO and VDD2 can be taken from the same 2.5 V source; however, it is best practice to isolate the VIO and VDD2 pins using separate traces and also to decouple each pin separately. The 5 V and 2.5 V supplies required for the AD7625 can be generated using Analog Devices, Inc.
PAGE 19
Data Sheet AD7625 DIGITAL INTERFACE Conversion Control The clock DCO± is a buffered copy of CLK± and is synchronous to the data, D±, which is updated on the falling edge of DCO+ (tD). By maintaining good propagation delay matching between D± and DCO± through the board and the digital host, DCO± can be used to latch D± with good timing margin for the shift register. All analog-to-digital conversions are controlled by the CNV signal.
PAGE 20
AD7625 Data Sheet Self-Clocked Interface Mode The digital operation of the AD7625 in self-clocked interface mode is shown in Figure 30. This interface mode reduces the number of wires between ADCs and the digital host to two LVDS pairs per AD7625 (CLK± and D±) or to a single pair if sharing a common CLK± using multiple AD7625 devices. Self-clocked interface mode facilitates the design of boards that use multiple AD7625 devices.
PAGE 21
Data Sheet AD7625 APPLICATIONS INFORMATION LAYOUT, DECOUPLING, AND GROUNDING When laying out the printed circuit board (PCB) for the AD7625, follow the practices described in this section to obtain the maximum performance from the converter. supply to Pin 19 and Pin 20 using a 100 nF capacitor to GND. This GND connection can be placed a short distance away from the exposed paddle. VIO Supply Decoupling Exposed Paddle Decouple the VIO supply applied to Pin 12 to ground at Pin 13.
PAGE 22
AD7625 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 32.
PAGE 23
Data Sheet AD7625 NOTES Rev.