Datasheet

AD7622
Rev. 0 | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06023-004
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
DGND
BYTESWAP
OB/2C
NC = NO CONNECT
SER/PAR
D0
D1
D2/DIVSCLK[0]
BUSY
D15
D14
D13
AD7622
D3/DIVSCLK[1]
D12
D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
PDBUF PDREF REFBUFIN TEMP AVDD IN+ AGND AGND NC IN– REFGND REF
NORMAL
WARP
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin
No.
Mnemonic Type
1
Description
1, 36,
41, 42
AGND P Analog Power Ground.
2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V.
3 DGND P Digital Power Ground.
4 BYTESWAP DI
Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5
OB/
2C
DI
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary;
when low, the MSB is inverted resulting in a twos complement output from its internal shift register.
6 WARP DI
Conversion Mode Selection. When WARP = high and
NORMAL = high, this selects wideband warp
mode with slightly improved linearity and THD. When WARP = high and
NORMAL = low, this selects
warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and
a minimum conversion rate must be applied to guarantee full specified accuracy.
7
NORMAL
DI
Conversion Mode Selection. When
NORMAL = low and WARP = low, this input selects normal mode
where full accuracy is maintained independent of the minimum conversion rate.
8
SER/
PAR
DI/O Serial/Parallel Selection Input.
When SER/
PAR = high, the serial interface is selected and some bits of the data bus are used as a
serial port; the remaining data bits are high impedance outputs.
When SER/
PAR = low, the parallel port is selected.
9, 10 D[0:1] DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of
the interface mode.
11, 12 D[2:3] DI/O
When SER/
PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
or DIVSCLK[0:1]
When SER/
PAR = high, serial clock division selection. When using serial master read after convert mode
(EXT/
INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated
serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
13 D4 DI/O
When SER/
PAR = low, this output is used as Bit 4 of the parallel port data output bus.
or EXT/
INT
When SER/
PAR = high, serial clock source select. This input is used to select the internally generated
(master) or external (slave) serial data clock.
When EXT/
INT = low, master mode. The internal serial clock is selected on SCLK output.
When EXT/
INT = high, slave mode. The output data is synchronized to an external clock signal,
gated by CS, connected to the SCLK input.