Datasheet

AD7621
Rev. 0 | Page 5 of 32
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
REF
= 2.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 31 and Figure 32)
Convert Pulse Width t
1
15 70
1
ns
Time Between Conversions (Warp
2
Mode/Normal Mode/Impulse Mode)
3
t
2
333/500/800 ns
CNVST Low to BUSY High Delay
t
3
23 ns
BUSY High All Modes (Except Master Serial Read After Convert) t
4
283/430/560 ns
Aperture Delay t
5
1 ns
End of Conversion to BUSY Low Delay t
6
10 ns
Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t
7
283/430/560 ns
Acquisition Time (Warp Mode/Normal Mode/Impulse Mode) t
8
50/70/50 ns
RESET Pulse Width t
9
15 ns
RESET Low to BUSY High Delay
4
t
38
10 ns
BUSY High Time from RESET Low
4
t
39
600 ns
PARALLEL INTERFACE MODES (Refer to Figure 33 and Figure 35)
CNVST Low to DATA Valid Delay
t
10
283/430/560 ns
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY Low Delay t
11
2 ns
Bus Access Request to DATA Valid t
12
20 ns
Bus Relinquish Time t
13
2 15 ns
MASTER SERIAL INTERFACE MODES
5
(Refer to Figure 37 and Figure 38)
CS Low to SYNC Valid Delay
t
14
10 ns
CS Low to Internal SCLK Valid Delay
5
t
15
10 ns
CS Low to SDOUT Delay
t
16
10 ns
CNVST Low to SYNC Delay
(Warp Mode/Normal Mode/Impulse Mode) t
17
12/137/263 ns
SYNC Asserted to SCLK First Edge Delay t
18
0.5 ns
Internal SCLK Period
6
t
19
8 12 ns
Internal SCLK High
6
t
20
2 ns
Internal SCLK Low
6
t
21
3 ns
SDOUT Valid Setup Time
6
t
22
1 ns
SDOUT Valid Hold Time
6
t
23
0 ns
SCLK Last Edge to SYNC Delay
6
t
24
0 ns
CS High to SYNC HI-Z
t
25
10 ns
CS High to Internal SCLK HI-Z
t
26
10 ns
CS High to SDOUT HI-Z
t
27
10 ns
BUSY High in Master Serial Read after Convert
6
t
28
See Table 4
CNVST Low to SYNC Asserted Delay (All Modes)
t
29
275/400/500 ns
SYNC Deasserted to BUSY Low Delay t
30
13 ns