Datasheet

AD7612 Data Sheet
Rev. A | Page 6 of 32
Parameter Symbol Min Typ Max Unit
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES
2
(See Figure 42,
Figure 43, and Figure 45)
External SDCLK, SCCLK Setup Time t
31
5 ns
External SDCLK Active Edge to SDOUT Delay t
32
2 18 ns
SDIN/SCIN Setup Time t
33
5 ns
SDIN/SCIN Hold Time t
34
5 ns
External SDCLK/SCCLK Period t
35
25 ns
External SDCLK/SCCLK High t
36
10 ns
External SDCLK/SCCLK Low t
37
10 ns
1
In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SDCLK First Edge Delay Minimum t
18
3 20 20 20 ns
Internal SDCLK Period Minimum t
19
30 60 120 240 ns
Internal SDCLK Period Maximum t
19
45 90 180 360 ns
Internal SDCLK High Minimum t
20
15 30 60 120 ns
Internal SDCLK Low Minimum t
21
10 25 55 115 ns
SDOUT Valid Setup Time Minimum t
22
4 20 20 20 ns
SDOUT Valid Hold Time Minimum t
23
5 8 35 90 ns
SDCLK Last Edge to SYNC Delay Minimum t
24
5 7 35 90 ns
BUSY High Width Maximum t
28
Warp Mode 1.65 2.35 3.75 6.53 µs
Normal Mode 1.9 2.6 4.00 6.78 µs
Impulse Mode 2.15 2.85 4.25 7.03 µs
NOTES
1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
1.6mA I
OL
500µA I
OH
1.4V
TO OUTPUT
PIN
C
L
60pF
0
6265-002
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, C
L
= 10 pF
0.8V
2V
2V
0.8V0.8V
2V
t
DELAY
t
DELAY
06265-003
Figure 3. Voltage Reference Levels for Timing