Datasheet

Data Sheet AD7612
Rev. A | Page 5 of 32
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V
REF
= 5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (See Figure 33 and Figure 34)
Convert Pulse Width t
1
10 ns
Time Between Conversions t
2
Warp Mode/Normal Mode/Impulse Mode
1
1.33/1.67/2 μs
CNVST Low to BUSY High Delay
t
3
35 ns
BUSY High All Modes (Except Master Serial Read After Convert) t
4
Warp Mode/Normal Mode/Impulse Mode 950/1250/1450 ns
Aperture Delay t
5
2 ns
End of Conversion to BUSY Low Delay t
6
10 ns
Conversion Time t
7
Warp Mode/Normal Mode/Impulse Mode 950/1250/1450 ns
Acquisition Time t
8
Warp Mode/Normal Mode/Impulse Mode 380 ns
RESET Pulse Width t
9
10 ns
PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)
CNVST Low to DATA Valid Delay
t
10
Warp Mode/Normal Mode/Impulse Mode 910/1160/1410 ns
DATA Valid to BUSY Low Delay t
11
20 ns
Bus Access Request to DATA Valid t
12
40 ns
Bus Relinquish Time t
13
2 15 ns
MASTER SERIAL INTERFACE MODES
2
(See Figure 39 and Figure 40)
CS Low to SYNC Valid Delay
t
14
10 ns
CS Low to Internal SDCLK Valid Delay
2
t
15
10 ns
CS Low to SDOUT Delay
t
16
10 ns
CNVST Low to SYNC Delay, Read During Convert
t
17
Warp Mode/Normal Mode/Impulse Mode 65/315/560 ns
SYNC Asserted to SDCLK First Edge Delay t
18
3 ns
Internal SDCLK Period
3
t
19
30 45 ns
Internal SDCLK High
3
t
20
15 ns
Internal SDCLK Low
3
t
21
10 ns
SDOUT Valid Setup Time
3
t
22
4 ns
SDOUT Valid Hold Time
3
t
23
5 ns
SDCLK Last Edge to SYNC Delay
3
t
24
5 ns
CS High to SYNC HI-Z
t
25
10 ns
CS High to Internal SDCLK HI-Z
t
26
10 ns
CS High to SDOUT HI-Z
t
27
10 ns
BUSY High in Master Serial Read After Convert
3
t
28
See Table 4
CNVST Low to SYNC Delay, Read After Convert
Warp Mode/Normal Mode/Impulse Mode t
29
830/1070/1310 ns
SYNC Deasserted to BUSY Low Delay t
30
25 ns