Datasheet

AD7612 Data Sheet
Rev. A | Page 24 of 32
INTERFACES
DIGITAL INTERFACE
The AD7612 has a versatile digital interface that can be set up
as either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7612
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In
most applications, the OVDD supply pin is connected to the host
system interface 2.5 V to 5.25 V digital supply. Finally, by using
the OB/
2C
input pin, both twos complement or straight binary
coding can be used.
Two signals,
CS
and
RD
, control the interface. When at least one of
these signals is high, the interface outputs are in high impedance.
Usually,
CS
allows the selection of each AD7612 in multi-circuit
applications and is held low in a single AD7612 design.
RD
is gen-
erally used to enable the conversion result on the data bus.
RESET
The RESET input is used to reset the AD7612. A rising edge on
RESET aborts the current conversion (if any) and tristates the
data bus. The falling edge of RESET resets the AD7612 and clears
the data bus and configuration register. See Figure 34 for the
RESET timing details.
t
9
t
8
RESET
DATA
BUS
BUSY
CNVST
0
6265-034
Figure 34. RESET Timing
PARALLEL INTERFACE
The AD7612 is configured to use the parallel interface when
SER/
PAR
is held low.
Master Parallel Interface
Data can be continuously read by tying
CS
and
RD
low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 35 details the timing for this mode.
t
1
BUSY
DATA
BUS
PREVIOUS CONVERSION DATA NEW DATA
CNVST
CS = RD = 0
t
10
t
4
t
11
t
3
06265-035
Figure 35. Master Parallel Data Timing for Reading (Continuous Read)
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 36 and
Figure 37, respectively. When the data is read during the conver-
sion, it is recommended that it is read only during the first half
of the conversion phase. This avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
CURRENT
CONVERSION
t
13
t
12
BUSY
DATA
BUS
RD
CS
06265-036
Figure 36. Slave Parallel Data Timing for Reading (Read After Convert)
PREVIOUS
CONVERSION
t
13
t
12
t
3
BUSY
DATA
BUS
CNVST,
RD
CS = 0
t
4
t
1
06265-037
Figure 37. Slave Parallel Data Timing for Reading (Read During Convert)