Datasheet

AD7610 Data Sheet
Rev. A | Page 10 of 32
Pin No. Mnemonic Type
1
Description
27 D14 or DI/O In parallel mode, this output is used as Bit 14 of the parallel port data output bus.
SCCLK
Serial Configuration Clock. In serial software configuration mode (SER/
PAR
= high, HW/
SW
= low) this input is
used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state
of the INVSCLK pin. See the
Software Configuration section.
28 D15 or DI/O In parallel mode, this output is used as Bit 15 of the parallel port data output bus.
SCCS
Serial Configuration Chip Select. In serial software configuration mode (SER/
PAR
= high, HW/
SW
= low) this
input enables the serial configuration port. See the
Software Configuration section.
29 BUSY DO Busy Output. Transitions high when a conversion is started, and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data ready clock signal. Note that in master read after convert mode (SER/
PAR
= high, EXT/
INT
= low,
RDC = low) the busy time changes according to
Table 4.
30 TEN DI
2
Input Range Select. Used in conjunction with BIPOLAR per the following:
Input Range BIPOLAR TEN
0 V to 5 V Low Low
0 V to 10 V Low High
±5 V High Low
±10 V High High
31
RD
DI
Read Data. When
CS
and
RD
are both low, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When
CS
and
RD
are both low, the interface parallel or serial output bus is enabled.
CS
is also
used to gate the external clock in slave serial mode (not used for serial programmable port).
33 RESET DI Reset Input. When high, reset the AD7610. Current conversion, if any, is aborted. The falling edge of RESET
resets the data outputs to all zero’s (with OB/
2C
= high) and clears the configuration register. See the Digital
Interface section. If not used, this pin can be tied to OGND.
34 PD DI
2
Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and conversions
are inhibited after the current one is completed. The digital interface remains active during power down.
35
CNVST
DI
Conversion Start. A falling edge on
CNVST
puts the internal sample-and-hold into the hold state and initiates
a conversion.
36 BIPOLAR DI
2
Input Range Select. See description for Pin 30.
37 REF AI/O Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V
on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally
supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is required with or without the
internal reference and buffer. See the
Reference Decoupling section.
38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane.
39 IN− AI Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground.
40 VCC P High Voltage Positive Supply. Normally +7 V to +15 V.
41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges).
43 IN+ AI Analog Input. Referenced to IN−.
45 TEMP AO Temperature Sensor Analog Output. Enabled when the internal reference is turned on (PDREF = PDBUF =
low). See the
Temperature Sensor section.
46 REFBUFIN AI Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low,
PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the
Voltage Reference Input section.
47 PDREF DI Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down, and an external reference must be used.
48 PDBUF DI Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
49 EPAD
3
NC
Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be soldered
to VEE.
1
AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
2
In serial configuration mode (SER/
PAR
= high, HW/
SW
= low), this input is programmed with the serial configuration register and this pin is a don’t care. See the
Hardware Configuration section and Software Configuration section.
3
LFCSP_VQ package only.