Datasheet

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AD7608 Data Sheet

Rev. A | Page 12 of 32

Pin No. Type12F11F

Mnemonic Description

DI RESET

Reset Input. When set to logic high, the rising edge of RESET resets the AD7608. Once t

WAKE-UP

has

elapsed, the part should receive a RESET pulse after power up. The RESET high pulse should be

typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If

a RESET pulse is applied during a read, the contents of the output registers resets to all zeros.

/SCLK

Parallel Data Read Control Input when Parallel Interface is Selected (

)/Serial Clock Input when the

Serial Interface is Selected (SCLK). When both AACS

and AARD

are logic low in parallel mode, the output

bus is enabled.

In parallel mode, two

AARD

pulses are required to read the full 18 bits of conversion results from each

channel. The first AARD

pulse outputs DB[17:2], the second AARD

pulse outputs DB[1:0].

In serial mode, this pin acts as the serial clock input for data transfers. The AACS

falling edge takes the

data output lines, D

OUT

A and D

OUT

B, out of three-state and clocks out the MSB of the conversion

result. The rising edge of SCLK clocks all subsequent data bits onto the D

OUT

A and D

OUT

B serial data

outputs. For further information, see the

Conversion Control section.

AACS

Chip Select. This active low logic input frames the data transfer. When both AACS

and AARD

are logic low

in parallel mode, the output bus, DB[15:0], is enabled and the conversion result is output on the

parallel data bus lines. In serial mode, the AACS

is used to frame the serial read transfer and clock out

the MSB of the serial output data.

14 DO BUSY

Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges

and indicates that the conversion process has started. The BUSY output remains high until the

conversion process for all channels is complete. The falling edge of BUSY signals that the conversion

data is being latched into the output data registers and is available to be read after a Time t

. Any

data read while BUSY is high must be complete before the falling edge of BUSY occurs. Rising edges

on CONVST A or CONVST B have no effect while the BUSY signal is high.

DO FRSTDATA

Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back

on either the parallel or serial interface. When the

AACS

input is high, the FRSTDATA output pin is in

three-state. The falling edge of

AACS

takes FRSTDATA out of three-state. In parallel mode, the falling

edge of

AARD

corresponding to the result of V1 then sets the FRSTDATA pin high indicating that the

result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low

following the third falling edge of

AARD

. In serial mode, FRSTDATA goes high on the falling edge of AACS

as this clocks out the MSB of V1 on D

OUT

A. It returns low on the 18

SCLK falling edge after the AACS

falling edge. See the

Conversion Control section for more details.

22 to 16

DO DB[6:0]

Parallel Output Data Bits, DB6 to DB0. When AAPAR

/SER SEL = 0, these pins act as three-state parallel

digital output pins. When

AACS

and AARD

are low, these pins are used to output DB8 to DB2 of the

conversion result during the first

AARD

pulse and output 0 during the second AARD

pulse. When AAPAR

/SER

SEL = 1, these pins should be tied to GND.

23 P V

DRIVE

Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the

operating voltage of the interface. This pin is nominally at the same supply as the supply of the host

interface (that is, DSP and FPGA).

DB7/D

OUT

Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (D

OUT

A). When AAPAR

/SER SEL = 0, this

pin acts as a three-state parallel digital output pin. When

AACS

and AARD

are low, this pin is used to

output DB9 of the conversion result. When AAPAR

/SER SEL = 1, this pin functions as D

OUT

A and outputs

serial conversion data. See the

Conversion Control section for further details.

DO DB8/D

OUT

Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (D

OUT

B). When AAPAR

/SER SEL = 0, this

pin acts as a three-state parallel digital output pin. When

AACS

and AARD

are low, this pin is used to

output DB10 of the conversion result. When AAPAR

/SER SEL = 1, this pin functions as D

OUT

B and

outputs serial conversion data. See the

Conversion Control section for further details.

31 to 27

DO DB[13:9]

Parallel Output Data Bits, DB13 to DB9. When AAPAR

/SER SEL = 0, these pins act as three-state parallel

digital output pins. When

AACS

and AARD

are low, these pins are used to output DB15 to DB11 of the

conversion result during the first AARD

pulse and output zero during the second AARD

pulse. When

AAPAR

/SER SEL = 1, these pins should be tied to GND.

32 DO/DI DB14

Parallel Output Data Bit 14 (DB14). When AAPAR

/SER SEL = 0, this pin act as three-state parallel digital

output pin. When

AACS

and AARD

are low, this pin is used to output DB16 of the conversion result during the

first

AARD

pulse and DB0 of the same conversion result during the second AARD

pulse. When AAPAR

/SER

SEL = 1, this pins should be tied to GND.

33 DO/DI DB15

Parallel Output Data Bit 15 (DB15). When AAPAR

/SER SEL = 0, this pin acts as three-state parallel digital

output pin. This pin is used to output DB17 of the conversion result during the first

AARD

pulse and

DB1 of the same conversion result during the second

AARD

pulse. When AAPAR

/SER SEL = 1, this pins

should be tied to GND.