8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC AD7608 Data Sheet FEATURES APPLICATIONS 8 simultaneously sampled inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.3 V to 5.
AD7608 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Converter Details ....................................................................... 19 Applications ....................................................................................... 1 Analog Input ............................................................................... 19 Companion Products .....................................................
Data Sheet AD7608 GENERAL DESCRIPTION The AD7608 is an 18-bit, 8-channel simultaneous sampling, analog-to-digital data acquisition system (DAS). The part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, an 18-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces.
AD7608 Data Sheet SPECIFICATIONS VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V; fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 2.
Data Sheet Parameter ANALOG INPUT Input Voltage Ranges Analog Input Current Input Capacitance 7 Input Impedance REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance7 Reference Output Voltage Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)7 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance7 Output Cod
AD7608 Data Sheet TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter PARALLEL/SERIAL/BYTE MODE tCYCLE Limit at TMIN, TMAX Min Typ Max Unit 5 µs 10.5 µs µs tWAKE-UP STANDBY 4.15 9.1 18.
Data Sheet Parameter t13 AD7608 Limit at TMIN, TMAX Min Typ Max Unit E ns ns ns ns t143 E A A 16 21 25 32 22 ns ns ns ns ns ns ns 23.5 17 14.5 11.5 MHz MHz MHz MHz 6 6 E A t18 A E A A E A A SERIAL READ OPERATION fSCLK Frequency of serial read clock VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE = 2.3 V to 2.
AD7608 Data Sheet Limit at TMIN, TMAX Min Typ Max Parameter t27 Unit Description Delay from RD falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25 V VDRIVE = 2.3 V to 2.7 V Delay from 16th SCLK falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25 V VDRIVE = 2.3 V to 2.7 V Delay from CS rising edge until FRSTDATA three-state enabled E A A 19 24 ns ns 17 22 24 ns ns ns t28 t29 E A A Sample tested during initial release to ensure compliance.
Data Sheet AD7608 t12 CS, RD t16 t13 V1 [17:2] V1 [1:0] V2 [17:2] V2 [1:0] V7 [17:2] V7 [1:0] V8 [17:2] t17 V8 [1:0] 08938-005 DATA: DB[15:0] FRSTDATA Figure 5. CS and RD Linked Parallel Mode E A E A A A CS t21 SCLK t19 t18 DOUTA, DOUTB t20 DB17 t22 DB16 DB15 t25 DB1 t23 DB0 t29 08938-006 t28 FRSTDATA Figure 6. Serial Read Operation (Channel 1) Rev.
AD7608 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4.
Data Sheet AD7608 64 63 62 61 60 59 58 V1GND V1 V2 V3 V2GND V4 V3GND V5 V4GND V6 V5GND V6GND V7 V7GND V8 V8GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 57 56 55 54 53 52 51 50 49 48 AVCC AVCC 1 ANALOG INPUT PIN 1 AGND 2 OS 0 3 DECOUPLING CAPACITOR PIN 47 AGND 46 REFGND POWER SUPPLY OS 1 4 45 REFCAPB GROUND PIN OS 2 5 44 REFCAPA PAR/SER SEL 6 DATA OUTPUT REFERENCE INPUT/OUTPUT 42 REFIN/REFOUT TOP VIEW (Not to Scale) RANGE 8 DIGITAL INPUT 43 REFGND AD7608 STBY 7 DI
AD7608 Data Sheet Pin No. 11 Type 1 DI 12 DI 12F1F Mnemonic RESET RD/SCLK E A A Description Reset Input. When set to logic high, the rising edge of RESET resets the AD7608. Once tWAKE-UP has elapsed, the part should receive a RESET pulse after power up. The RESET high pulse should be typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers resets to all zeros.
Data Sheet AD7608 Pin No. 34 Type 1 DI Mnemonic REF SELECT 36, 39 P REGCAP 42 REF REFIN/ REFOUT 43, 46 44, 45 REF REF 49, 51, 53, 55, 57, 59, 61, 63 50, 52, 54, 56, 58, 60, 62, 64 AI REFGND REFCAPA, REFCAPB V1 to V8 AI/ GND V1GND to V8GND 1 12F1F Description Internal/External Reference Selection Input. Logic input.
AD7608 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 4.0 3.5 AVCC, VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200 kSPS TA = 25°C ±10V RANGE SNR = 91.23dB SINAD = 91.17dB THD = 108.69dB 16384 POINT FFT fIN = 1kHz 60k 70k 80k 90k 100k Figure 12. Typical DNL, ±10 V Range –80 –100 –2.0 –2.5 –3.0 –140 –3.5 –4.
AD7608 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1.
AD7608 Data Sheet 105 4.0 90 AVCC, VDRIVE = 5V fSAMPLE CHANGES WITH OS RATE TA = 25°C INTERNAL REFERENCE ±5V RANGE 1k 10k 0 ±5V RANGE –0.8 –1.6 ±10V RANGE –2.4 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE 100k INPUT FREQUENCY (Hz) –4.0 –40 –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) Figure 20. SNR vs. Input Frequency for Different Oversampling Rates, ±5 V Range Figure 23. Bipolar Zero Code Error vs.
Data Sheet AD7608 110 22 20 ±5V RANGE 95 90 AVCC, VDRIVE = 5V TA = 25 °C INTERNAL REFERENCE fSAMPLE SCALES WITH OS RATIO fIN SCALES WITH OS RATIO 85 80 NO OS OS × 2 OS × 4 OS × 8 OS × 16 OS × 32 OS × 64 OVERSAMPLING RATIO 18 16 14 12 AVCC, VDRIVE = 5V 10 TA = 25°C INTERNAL REFERENCE fSAMPLE VARIES WITH OS RATE 8 NO OS OS2 OS4 OS8 AVCC = 5.25V AVCC = 5V 2.5000 2.4995 AVCC = 4.75V 2.4990 2.4980 –40 –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) 08938-129 2.4985 Figure 27.
AD7608 Data Sheet TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, at ½ LSB below the first code transition; and full scale, at ½ LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Data Sheet AD7608 THEORY OF OPERATION CONVERTER DETAILS Analog Input Clamp Protection The AD7608 is a data acquisition system that employs a high speed, low power, charge redistribution, successive approximation analog-to-digital converter (ADC) and allows the simultaneous sampling of eight analog input channels. The analog inputs on the AD7608 can accept true bipolar input signals. The RANGE pin is used to select either ±10 V or ±5 V as the input range. The AD7608 operates from a single 5 V supply.
AD7608 Data Sheet Analog Input Antialiasing Filter An analog antialiasing filter (a second-order Butterworth) is also provided on the AD7608. Figure 34 and Figure 35 show the frequency and phase response, respectively, of the analog antialiasing filter. In the ±5 V range, the −3 dB frequency is typically 15 kHz. In the ±10 V range, the −3 dB frequency is typically 23 kHz. 5 ±5V RANGE –15 –20 –25 –30 –35 ±10V RANGE –40 +25 +85 0.
Data Sheet AD7608 INTERNAL/EXTERNAL REFERENCE Internal Reference Mode The AD7608 contains an on-chip 2.5 V band gap reference. The REFIN/REFOUT pin allows access to the 2.5 V reference that generates the on-chip 4.5 V reference internally, or it allows an external reference of 2.5 V to be applied to the AD7608. An externally applied reference of 2.5 V is also gained up to 4.5 V, using the internal buffer. This 4.5 V buffered reference is the reference used by the SAR ADC.
AD7608 Data Sheet TYPICAL CONNECTION DIAGRAM The power-down mode is selected through the state of the RANGE pin when the STBY pin is low. Table 7 shows the configurations required to choose the desired power-down mode. When the AD7608 is placed in standby mode, the current consumption is 8 mA maximum and power-up time is approximately 100 µs because the capacitor on the REFCAPA and REFCAPB pins must charge up.
Data Sheet AD7608 CONVERSION CONTROL Simultaneously Sampling Two Sets of Channels Simultaneous Sampling on All Analog Input Channels The AD7608 also allows the analog input channels to be sampled simultaneously in two sets. This can be used in powerline protection and measurement systems to compensate for phase differences introduced by PT and CT transformers. In a 50 Hz system, this allows for up to 9° of phase compensation; and in a 60 Hz system, it allows for up to 10° of phase compensation.
AD7608 Data Sheet DIGITAL INTERFACE The AD7608 provides two interface options: a parallel interface and high speed serial interface. The required interface mode is selected via the PAR/SER SEL pin. The CS signal can be permanently tied low, and the RD signal can be used to access the conversion results as shown in Figure 4.
Data Sheet AD7608 SERIAL INTERFACE (PAR/SER SEL = 1) The SCLK input signal provides the clock source for the serial read operation. CS goes low to access the data from the AD7608. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the 18-bit conversion result. This MSB is valid on the first falling edge of the SCLK after the CS falling edge. The subsequent 17 data bits are clocked out of the AD7608 on the SCLK rising edge. Data is valid on the SCLK falling edge.
AD7608 Data Sheet Figure 44 shows that the conversion time extends as the oversampling rate is increased, and the BUSY signal lengthens for the different oversampling rates. For example, a sampling frequency of 10 kSPS yields a cycle time of 100 µs. Figure 44 shows OS × 2 and OS × 4; for a 10 kSPS example, there is adequate cycle time to further increase the oversampling rate and yield greater improvements in SNR performance.
Data Sheet AD7608 NO OVERSAMPLING 1377 1170 1208 1200 1001 2176 2000 708 1500 1000 648 0 411 400 –2 –1 0 CODE 146 82 66 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 CODE 2 3 4 5 21 5 6 7 0 1 2 2 3 4 8 9 Figure 46. Histogram of Codes—No OS (18 Codes) 2000 OVERSAMPLING BY 2 1759 1800 1600 1524 1397 1400 1200 1065 OVERSAMPLING BY 16 3947 4000 NUMBER OF OCCURENCES 0 –3 44 4500 188 3 78 4 Figure 49.
AD7608 Data Sheet 7000 OVERSAMPLING BY 64 0 6489 AVCC = 5V VDRIVE = 5V TA = 25°C ±10V RANGE OS BY 4 –10 –20 5000 ATTENUATION (dB) NUMBER OF OCCURENCES 6000 4000 3000 2000 1238 –30 –40 –50 –60 –70 –80 1000 465 1 –20 10M –30 –40 –50 –60 –70 –80 –90 –100 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 55. Digital Filter Response for OS × 8 –30 0 AVCC = 5V VDRIVE = 5V TA = 25°C ±10V RANGE OS BY 16 –40 –10 –50 –20 –70 –80 10k 100k FREQUENCY (Hz) 1M 10M Figure 53.
Data Sheet AD7608 0 –20 –20 ATTENUATION (dB) –30 –40 –50 –60 –70 –80 –30 –40 –50 –60 –70 –80 –90 1k 10k 100k 1M FREQUENCY (Hz) 10M Figure 57. Digital Filter Response for OS × 32 –100 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 58. Digital Filter Response for OS × 64 Rev.
AD7608 Data Sheet LAYOUT GUIDELINES The printed circuit board that houses the AD7608 should be designed so that the analog and digital sections are separated and confined to different areas of the board. If the AD7608 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point: a star ground point should be established as close as possible to the AD7608. Good connections should be made to the ground plane.
Data Sheet AD7608 To ensure good device-to-device performance matching, in a system that contains multiple AD7608 devices, a symmetrical layout between the AD7608 devices is important. Figure 61 shows a layout with two devices. The AVCC supply plane runs to the right of both devices. The VDRIVE supply track runs to the left of the two devices. The reference chip is positioned between both the two devices and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 to U2.
AD7608 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 16 0.08 COPLANARITY VIEW A 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 62.
