Datasheet

AD7607 Data Sheet
Rev. B | Page 6 of 32
TIMING SPECIFICATIONS
AV
CC
= 4.75 V to 5.25 V, V
DRIVE
= 2.3 V to 5.25 V, V
REF
= 2.5 V external reference/internal reference, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 3.
Limit at T
MIN
, T
MAX
Parameter Min Typ Max Unit Description
PARALLEL/SERIAL/BYTE MODE
t
CYCLE
1/throughput rate
5 µs Parallel mode, reading during or after conversion; or serial mode (V
DRIVE
=
3.3 V to 5.25 V), reading during a conversion using D
OUT
A and D
OUT
B lines
5 µs Serial mode reading during conversion; V
DRIVE
= 2.7 V
9.1
µs
Serial mode reading after a conversion; V
DRIVE
= 2.3 V, D
OUT
A and D
OUT
B lines
t
CONV
Conversion time
3.45 4 4.15 µs Oversampling off
7.87 9.1 µs Oversampling by 2
16.05 18.8 µs Oversampling by 4
33 39 µs Oversampling by 8
66 78 µs Oversampling by 16
133 158 µs Oversampling by 32
257 315 µs Oversampling by 64
t
WAKE-UP STANDBY
100 µs
STBY
rising edge to CONVST x rising edge; power-up time from
standby mode
t
WAKE-UP SHUTDOWN
Internal Reference 30 ms
STBY
rising edge to CONVST x rising edge; power-up time from
shutdown mode
External Reference 13 ms
STBY
rising edge to CONVST x rising edge; power-up time from
shutdown mode
t
RESET
50 ns RESET high pulse width
t
OS_SETUP
20 ns BUSY to OS x pin setup time
t
OS_HOLD
20 ns BUSY to OS x pin hold time
t
1
40 ns CONVST x high to BUSY high
t
2
25 ns Minimum CONVST x low pulse
t
3
25 ns Minimum CONVST x high pulse
t
4
0 ns BUSY falling edge to
CS
falling edge setup time
t
5
2
0.5
ms
Maximum delay allowed between CONVST A, CONVST B rising edges
t
6
25 ns Maximum time between last
CS
rising edge and BUSY falling edge
t
7
25 ns Minimum delay between RESET low to CONVST x high
PARALLEL/BYTE READ
OPERATION
t
8
0 ns
CS
to
RD
setup time
t
9
0 ns
CS
to
RD
hold time
t
10
RD
low pulse width
16 ns V
DRIVE
above 4.75 V
21 ns V
DRIVE
above 3.3 V
25 ns V
DRIVE
above 2.7 V
32 ns V
DRIVE
above 2.3 V
t
11
15 ns
RD
high pulse width
t
12
22 ns
CS
high pulse width (see Figure 5);
CS
and
RD
linked