Datasheet

AD7607 Data Sheet
Rev. B | Page 24 of 32
DIGITAL INTERFACE
The AD7607 provides three interface options: a parallel inter-
face, a high speed serial interface, and a parallel byte interface.
The required interface mode is selected via the
PAR
/SER/BYTE
SEL and the DB15/BYTE SEL pins.
Table 8. Interface Mode Selection
PAR
/SER/BYTE SEL
DB15 Interface Mode
0 0 Parallel interface mode
1 0 Serial interface mode
1 1 Parallel byte interface mode
Interface mode operation is discussed in the following sections.
PARALLEL INTERFACE (
PAR
/SER/BYTE SEL = 0)
Data can be read from the AD7607 via the parallel data bus with
standard
CS
and
RD
signals. To read the data over the parallel bus,
the
PAR
/SER/BYTE SEL pin should be tied low. The
CS
and
RD
input signals are internally gated to enable the conversion result
onto the data bus. The data lines, DB15 to DB0, leave their high
impedance state when both
CS
and
RD
are logic low. When
CS
and
RD
are low, DB15 and DB14 are used to output a sign
extended bit of the MSB (DB13) of the conversion result.
AD7607
14
BUSY
12
RD
33:16
DB[15:0]
13
CS
DIGITAL
HOST
INTERRUPT
08096-041
Figure 41. Interface Diagram—One AD7607 Using the Parallel Bus,
with
CS
and
RD
Shorted Together
The rising edge of the
CS
input signal tristates the bus, and the
falling edge of the
CS
input signal takes the bus out of the high
impedance state.
CS
is the control signal that enables the data
lines; it is the function that allows multiple AD7607 devices to
share the same parallel data bus.
The
CS
signal can be permanently tied low, and the
RD
signal
can be used to access the conversion results as shown in
Figure 4.
A read operation of new data can take place after the BUSY
signal goes low (see Figure 2); or, alternatively, a read operation
of data from the previous conversion process can take place
while BUSY is high (see Figure 3).
The
RD
pin is used to read data from the output conversion results
register. Applying a sequence of
RD
pulses to the
RD
pin of the
AD7607 clocks the conversion results out from each channel
onto the parallel output bus, DB[15:0], in ascending order.
The first
RD
falling edge after BUSY goes low clocks out the
conversion result from Channel V1. The next
RD
falling edge
updates the bus with the V2 conversion result, and so on. The
eighth falling edge of
RD
clocks out the conversion result for
Channel V8. When the
RD
signal is logic low, it enables the data
conversion result from each channel to be transferred to the
digital host (DSP, FPGA).
When there is only one AD7607 in a system/board and it does not
share the parallel bus, data can be read using just one control
signal from the digital host. The
CS
and
RD
signals can be tied
together, as shown in
Figure 5. In this case, the data bus comes
out of three-state on the falling edge of
CS
/
RD
. The combined
CS
and
RD
signal allows the data to be clocked out of the AD7607 and
to be read by the digital host. In this case,
CS
is used to frame
the data transfer of each data channel.
PARALLEL BYTE INTERFACE (
PAR
/SER/BYTE SEL = 1,
DB15 = 1)
Parallel byte interface mode operates much like the parallel
interface mode, except that each channel conversion result is read
out in two 8-bit transfers. Therefore, 16
RD
pulses are required to
read all eight conversion results from the AD7607. To configure the
AD7607 to operate in parallel byte interface mode, the
PAR
/SER/
BYTE SEL and BYTE SEL/DB15 pins should be tied to logic high
(see
Table 8). DB[7:0] are used to transfer the data to the digital
host. DB0 is the LSB of the data transfer, and DB7 is the MSB of
the data transfer. In parallel byte mode, DB14 acts as an HBEN
pin. When the DB14/HBEN pin is tied to logic high, the most
significant byte (MSB) of the conversion result is output first,
followed by the LSB byte of the conversion result. When
DB14/HBEN is tied to logic low, the LSB byte of the conversion
result is output first, followed by the MSB byte of the conversion
result. The FRSTDATA pin remains high until the entire 14 bits
of the conversion result from V1 is read. If the MSB byte is always
to be read first, the HBEN pin should be set high and remain
high. If the LSB byte is always to be read first, the HBEN pin
should be set low and remain low. In this circumstance, the
MSB byte contains two sign extended bits in the two MSB
positions.
SERIAL INTERFACE (
PAR
/SER/BYTE SEL = 1)
To read data back from the AD7607 over the serial interface,
the
PAR
/SER/BYTE SEL pin must be tied high. The
CS
and
SCLK signals are used to transfer data from the AD7607. The
AD7607 has two serial data output pins, D
OUT
A and D
OUT
B.
Data can be read back from the AD7607 using one or both of
these D
OUT
lines. For the AD7607, conversion results from
Channel V1 to Channel V4 first appear on D
OUT
A, and
conversion results from Channel V5 to Channel V8 first appear
on D
OUT
B.
The
CS
falling edge takes the data output lines, D
OUT
A and D
OUT
B,
out of three-state and clocks out the MSB of the conversion result.
The rising edge of SCLK clocks all subsequent data bits onto the
serial data outputs, D
OUT
A and D
OUT
B. The
CS
input can be held
low for the entire serial read, or it can be pulsed to frame each
channel read of 14 SCLK cycles.