Datasheet

Data Sheet AD7606/AD7606-6/AD7606-4
Rev. C | Page 9 of 36
Limit at T
MIN
, T
MAX
(0.1 × V
DRIVE
and
0.9 × V
DRIVE
Logic Input Levels)
Limit at T
MIN
, T
MAX
(0.3 × V
DRIVE
and
0.7 × V
DRIVE
Logic Input Levels)
Parameter Min Typ Max Min Typ Max Unit Description
t
27
Delay from
RD
falling edge to FRSTDATA low
19 22 ns V
DRIVE
= 3.3 V to 5.25V
24 29 ns V
DRIVE
= 2.3 V to 2.7V
t
28
Delay from 16
th
SCLK falling edge to FRSTDATA low
17 20 ns V
DRIVE
= 3.3 V to 5.25V
22 27 ns V
DRIVE
= 2.3 V to 2.7V
t
29
24 29 ns
Delay from
CS
rising edge until FRSTDATA three-
state enabled
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DRIVE
) and timed from a voltage level of 1.6 V.
2
In oversampling mode, typical t
CONV
for the AD7606-6 and AD7606-4 can be calculated using ((N × t
CONV
) + ((N − 1) × 1 µs)). N is the oversampling ratio. For the AD7606-6,
t
CONV
= 3 µs; and for the AD7606-4, t
CONV
= 2 µs.
3
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets.
4
A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams
t
CYCLE
t
3
t
5
t
2
t
4
t
1
t
7
t
RESET
t
CONV
CONVST A,
CONVST B
CONVST A,
CONVST B
BUSY
CS
RESET
08479-002
Figure 2. CONVST Timing—Reading After a Conversion
t
CYCLE
t
3
t
5
t
6
t
2
t
1
t
CONV
CONVST A,
CONVST B
CONVST A,
CONVST B
BUSY
CS
t
7
t
RESET
RESET
08479-003
Figure 3. CONVST Timing—Reading During a Conversion