Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - ADC 16 Bit LQFP 64

8-/6-/4-Channel DAS with 16-

Bit, Bipolar

Input, Simultaneous Sampling ADC

Data Sheet

AD7606/AD7606-6/AD7606-4

Rev. C

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

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Tel: 781.329.4700

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FEATURES

8/6/4 simultaneously sampled inputs

True bipolar analog input ranges: ±10 V, ±5 V

Single 5 V analog supply and 2.3 V to 5 V V

DRIVE

Fully integrated data acquisition solution

Analog input clamp protection

Input buffer with 1 MΩ analog input impedance

Second-order antialiasing analog filter

On-chip accurate reference and reference buffer

16-bit ADC with 200 kSPS on all channels

Oversampling capability with digital filter

Flexible parallel/serial interface

SPI/QSPI™/MICROWIRE™/DSP compatible

Performance

7 kV ESD rating on analog input channels

95.5 dB SNR, −107 dB THD

±0.5 LSB INL, ±0.5 LSB DNL

Low power: 100 mW

Standby mode: 25 mW

64-lead LQFP package

APPLICATIONS

Power-line monitoring and protection systems

Multiphase motor control

Instrumentation and control systems

Multiaxis positioning systems

Data acquisition systems (DAS)

Table 1. High Resolution, Bipolar Input, Simultaneous

Sampling DAS Solutions

Resolution

Single-

Ended

Inputs

True

Differential

Inputs

Number of

Simultaneous

Sampling Channels

18 Bits AD7608 AD7609 8

16 Bits AD7606 8

AD7606-6 6

AD7606-4 4

14 Bits AD7607 8

FUNCTIONAL BLOCK DIAGRAM

V1GND

1MΩ

CLAMP

SECOND-

ORDER LPF

T/H

V2GND

1MΩ

CLAMP

SECOND-

ORDER LPF

T/H

V3GND

1MΩ

CLAMP

SECOND-

ORDER LPF

T/H

V4GND

1MΩ

CLAMP

SECOND-

ORDER LPF

T/H

V5GND

1MΩ

CLAMP

SECOND-

ORDER LPF

T/H

V6GND

1MΩ

CLAMP

SECOND-

ORDER LPF

T/H

V7GND

1MΩ

CLAMP

SECOND-

ORDER LPF

T/H

V8GND

1MΩ

CLAMP

SECOND-

ORDER LPF

T/H

8:1

MUX

AGND

BUSY

FRSTDATA

CONVST A CONVST B

RESET

RANGE

CONTROL

INPUTS

CLK OSC

REFIN/REFOUT

REF SELECT

AGND

OS 2

OS 1

OS 0

OUT

RD/SCLK

PAR/SER/BYTE SEL

DRIVE

16-BIT

SAR

DIGITAL

FILTER

PARALLEL/

SERIAL

INTERFACE

2.5V

REF

REFCAPB

REFCAPA

SERIAL

PARALLEL

REGCAP

2.5V

LDO

REGCAP

2.5V

LDO

DB[15:0]

AD7606

08479-001

Figure 1.

Summary of content (36 pages)

PAGE 1
8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC AD7606/AD7606-6/AD7606-4 Data Sheet FEATURES APPLICATIONS 8/6/4 simultaneously sampled inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.
PAGE 2
AD7606/AD7606-6/AD7606-4 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input ............................................................................... 22 Applications ....................................................................................... 1 ADC Transfer Function ............................................................. 23 Functional Block Diagram ...................................
PAGE 3
Data Sheet AD7606/AD7606-6/AD7606-4 GENERAL DESCRIPTION The AD76061/AD7606-6/AD7606-4 are 16-bit, simultaneous sampling, analog-to-digital data acquisition systems (DAS) with eight, six, and four channels, respectively. Each part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, a 16-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, a 2.
PAGE 4
AD7606/AD7606-6/AD7606-4 Data Sheet SPECIFICATIONS VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 2.
PAGE 5
Data Sheet Parameter ANALOG INPUT Input Voltage Ranges Analog Input Current Input Capacitance 7 Input Impedance REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance7 Reference Output Voltage Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)7 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance7 Output Cod
PAGE 6
AD7606/AD7606-6/AD7606-4 Parameter Power Dissipation Normal Mode (Static) Normal Mode (Operational) 8 Data Sheet Test Conditions/Comments AD7606 fSAMPLE = 200 kSPS AD7606 AD7606-6 AD7606-4 Standby Mode Shutdown Mode Min Typ Max Unit 80 115.5 mW 100 90 75 25 10 142 126 111 42 31.5 mW mW mW mW µW Temperature range for the B version is −40°C to +85°C. The AD7606 is operational up to 125°C with throughput rates ≤ 160 kSPS, and the SNR typically reduces by 0.7 dB at 125°C.
PAGE 7
Data Sheet AD7606/AD7606-6/AD7606-4 TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter PARALLEL/SERIAL/BYTE MODE tCYCLE Limit at TMIN, TMAX (0.1 × VDRIVE and 0.9 × VDRIVE Logic Input Levels) Min Typ Max Limit at TMIN, TMAX (0.3 × VDRIVE and 0.7 × VDRIVE Logic Input Levels) Min Typ Max Unit 5 5 µs 9.7 9.4 10.7 µs µs 4.15 9.1 18.
PAGE 8
AD7606/AD7606-6/AD7606-4 Parameter t13 Data Sheet Limit at TMIN, TMAX (0.1 × VDRIVE and 0.9 × VDRIVE Logic Input Levels) Min Typ Max Limit at TMIN, TMAX (0.3 × VDRIVE and 0.7 × VDRIVE Logic Input Levels) Min Typ Max Unit 16 20 25 30 19 24 30 37 ns ns ns ns 16 21 25 32 19 24 30 37 t144 t15 t16 t17 22 22 ns ns ns ns ns ns ns 23.5 17 14.5 11.5 20 15 12.
PAGE 9
Data Sheet AD7606/AD7606-6/AD7606-4 Limit at TMIN, TMAX (0.1 × VDRIVE and 0.9 × VDRIVE Logic Input Levels) Min Typ Max Parameter t27 Limit at TMIN, TMAX (0.3 × VDRIVE and 0.7 × VDRIVE Logic Input Levels) Min Typ Max Unit 19 24 22 29 ns ns 17 22 24 20 27 29 ns ns ns Description Delay from RD falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25V VDRIVE = 2.3 V to 2.7V Delay from 16th SCLK falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25V VDRIVE = 2.3 V to 2.
PAGE 10
AD7606/AD7606-6/AD7606-4 Data Sheet CS t8 t16 t13 t14 DATA: DB[15:0] INVALID t24 FRSTDATA V1 V2 t26 V3 t17 t15 V4 V7 V8 t27 t29 08479-004 RD t9 t11 t10 Figure 4. Parallel Mode, Separate CS and RD Pulses t12 CS AND RD t16 t13 DATA: DB[15:0] V2 V3 V4 V5 V6 V7 t17 V8 08479-005 V1 FRSTDATA Figure 5. CS and RD, Linked Parallel Mode CS t20 t19 t18 DOUTA, DOUTB DB15 t22 DB14 DB13 t23 DB1 DB0 t25 t29 t28 FRSTDATA Figure 6.
PAGE 11
Data Sheet AD7606/AD7606-6/AD7606-4 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 4.
PAGE 12
AD7606/AD7606-6/AD7606-4 Data Sheet 64 63 62 61 60 59 58 V1GND V1 V2 V3 V2GND V4 V3GND V5 V4GND V6 V5GND V6GND V7 V7GND V8 V8GND PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 57 56 55 54 53 52 51 50 49 AVCC 1 ANALOG INPUT 48 PIN 1 AGND 2 OS 0 3 DECOUPLING CAP PIN AVCC 47 AGND 46 REFGND POWER SUPPLY OS 1 4 45 REFCAPB GROUND PIN OS 2 5 44 REFCAPA AD7606 43 REFGND TOP VIEW (Not to Scale) 42 REFIN/REFOUT 41 AGND CONVST A 9 40 AGND CONVST B 10 39 REGCAP RESET 11
PAGE 13
64 63 62 61 60 59 58 V1GND V1 V2 AGND V2GND AGND AGND V3 AGND V4 V3GND V4GND AGND AGND AGND AD7606/AD7606-6/AD7606-4 AGND Data Sheet 57 56 55 54 53 52 51 50 49 AVCC 1 ANALOG INPUT 48 PIN 1 AGND 2 OS 0 3 DECOUPLING CAP PIN AVCC 47 AGND 46 REFGND POWER SUPPLY OS 1 4 45 REFCAPB GROUND PIN OS 2 5 44 REFCAPA REFGND DATA OUTPUT PAR/SER/BYTE SEL 6 AD7606-4 43 STBY 7 TOP VIEW (Not to Scale) 42 REFIN/REFOUT 41 AGND CONVST A 9 40 AGND CONVST B 10 39 REGCAP RESET 11
PAGE 14
AD7606/AD7606-6/AD7606-4 Data Sheet Pin No. 8 Type 1 DI AD7606 RANGE Mnemonic AD7606-6 RANGE AD7606-4 RANGE 9, 10 DI CONVST A, CONVST B CONVST A, CONVST B CONVST A, CONVST B 11 DI RESET RESET RESET 12 DI RD/SCLK RD/SCLK RD/SCLK 13 DI CS CS CS 14 DO BUSY BUSY BUSY 15 DO FRSTDATA FRSTDATA FRSTDATA Description Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels.
PAGE 15
Data Sheet AD7606/AD7606-6/AD7606-4 Pin No.
PAGE 16
AD7606/AD7606-6/AD7606-4 Data Sheet Pin No.
PAGE 17
Data Sheet AD7606/AD7606-6/AD7606-4 TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 –40 –60 AVCC, VDRIVE = 5V FSAMPLE = 200kSPS TA = 25°C INTERNAL REFERENCE ±10V RANGE 1.5 1.0 0.5 INL (LSB) –80 –100 0 –0.5 –120 –1.0 –140 –1.5 –160 0 10k 20k 30k 40k 50k 60k 70k 80k 90k 100k INPUT FREQUENCY (Hz) –2.0 08479-011 –180 0 1.0 –60 40k 50k 60k AVCC, VDRIVE = 5V FSAMPLE = 200kSPS TA = 25°C INTERNAL REFERENCE ±10V RANGE 0.8 0.6 0.4 DNL (LSB) AMPLITUDE (dB) –40 30k Figure 14.
PAGE 18
AD7606/AD7606-6/AD7606-4 0.50 8 NFS/PFS CHANNEL MATCHING (LSB) 0.75 0.25 0 –0.25 –0.50 –0.75 4 NFS ERROR 2 0 –2 –4 –6 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 –10 –40 20 35 50 65 80 10 15 8 PFS/NFS ERROR (%FS) 10 NFS ERROR (LSB) 5 Figure 20.
PAGE 19
AD7606/AD7606-6/AD7606-4 98 4 96 3 5V RANGE 94 2 92 SNR (dB) 1 10V RANGE 0 90 88 –1 84 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE –3 –4 –40 –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) 82 80 10 Figure 23.
PAGE 20
AD7606/AD7606-6/AD7606-4 Data Sheet 22 100 ±10V RANGE 20 AVCC SUPPLY CURRENT (mA) 94 ±5V RANGE 92 90 88 86 84 AVCC, VDRIVE = 5V TA = 25°C 82 INTERNAL REFERENCE FSAMPLE SCALES WITH OS RATIO 80 OFF OS2 OS4 OS8 OS16 OS32 08479-026 OS64 OVERSAMPLING RATIO 18 16 14 12 AVCC, VDRIVE = 5V 10 TA = 25°C INTERNAL REFERENCE FSAMPLE VARIES WITH OS RATE 8 NO OS OS2 OS4 OS8 Figure 29. Dynamic Range vs. Oversampling Rate REFOUT VOLTAGE (V) POWER SUPPLY REJECTION RATIO (dB) AVCC = 5.25V AVCC = 5V 2.5000 2.
PAGE 21
Data Sheet AD7606/AD7606-6/AD7606-4 TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, at ½ LSB below the first code transition; and full scale, at ½ LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
PAGE 22
AD7606/AD7606-6/AD7606-4 Data Sheet THEORY OF OPERATION CONVERTER DETAILS Analog Input Clamp Protection The AD7606/AD7606-6/AD7606-4 are data acquisition systems that employ a high speed, low power, charge redistribution, successive approximation analog-to-digital converter (ADC) and allow the simultaneous sampling of eight/six/four analog input channels. The analog inputs on the AD7606/AD7606-6/AD7606-4 can accept true bipolar input signals.
PAGE 23
Data Sheet AD7606/AD7606-6/AD7606-4 R R C Vx CLAMP VxGND CLAMP 1MΩ 1MΩ 08479-034 ANALOG INPUT SIGNAL hold (that is, the delay time between the external CONVST x signal and the track-and-hold actually going into hold) is well matched, by design, across all eight track-and-holds on one device and from device to device. This matching allows more than one AD7606/AD7606-6/AD7606-4 device to be sampled simultaneously in a system. RFB AD7606 RFB Figure 36.
PAGE 24
AD7606/AD7606-6/AD7606-4 Data Sheet INTERNAL/EXTERNAL REFERENCE Internal Reference Mode The AD7606/AD7606-6/AD7606-4 contain an on-chip 2.5 V band gap reference. The REFIN/REFOUT pin allows access to the 2.5 V reference that generates the on-chip 4.5 V reference internally, or it allows an external reference of 2.5 V to be applied to the AD7606/AD7606-6/AD7606-4. An externally applied reference of 2.5 V is also gained up to 4.5 V, using the internal buffer. This 4.
PAGE 25
Data Sheet AD7606/AD7606-6/AD7606-4 TYPICAL CONNECTION DIAGRAM The power-down mode is selected through the state of the RANGE pin when the STBY pin is low. Table 7 shows the configurations required to choose the desired power-down mode. When the AD7606/AD7606-6/AD7606-4 are placed in standby mode, the current consumption is 8 mA maximum and powerup time is approximately 100 µs because the capacitor on the REFCAPA and REFCAPB pins must charge up.
PAGE 26
AD7606/AD7606-6/AD7606-4 Data Sheet CONVERSION CONTROL transformers. In a 50 Hz system, this allows for up to 9° of phase compensation; and in a 60 Hz system, it allows for up to 10° of phase compensation. Simultaneous Sampling on All Analog Input Channels The AD7606/AD7606-6/AD7606-4 allow simultaneous sampling of all analog input channels. All channels are sampled simultaneously when both CONVST pins (CONVST A, CONVST B) are tied together.
PAGE 27
Data Sheet AD7606/AD7606-6/AD7606-4 DIGITAL INTERFACE The AD7606/AD7606-6/AD7606-4 provide three interface options: a parallel interface, a high speed serial interface, and a parallel byte interface. The required interface mode is selected via the PAR/SER/BYTE SEL and DB15/BYTE SEL pins. Table 8.
PAGE 28
AD7606/AD7606-6/AD7606-4 Data Sheet The CS falling edge takes the data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data outputs, DOUTA and DOUTB. The CS input can be held low for the entire serial read operation, or it can be pulsed to frame each channel read of 16 SCLK cycles. Figure 46 shows a read of eight simultaneous conversion results using two DOUT lines on the AD7606.
PAGE 29
Data Sheet AD7606/AD7606-6/AD7606-4 DIGITAL FILTER tCYCLE The AD7606/AD7606-6/AD7606-4 contain an optional digital first-order sinc filter that should be used in applications where slower throughput rates are used or where higher signal-to-noise ratio or dynamic range is desirable. The oversampling ratio of the digital filter is controlled using the oversampling pins, OS [2:0] (see Table 9). OS 2 is the MSB control bit, and OS 0 is the LSB control bit.
PAGE 30
AD7606/AD7606-6/AD7606-4 Data Sheet NO OVERSAMPLING 900 FSAMPLE = 200kSPS AVCC = 5V 800 VDRIVE = 2.5V 928 887 700 600 1263 1000 783 800 600 400 500 200 0 300 97 100 0 3 –3 –2 0 1 2 3 CODE (LSB) 0 1 0 0 2 3 1400 OVERSAMPLING BY 16 FSAMPLE = 12.5kSPS 1200 AVCC = 5V VDRIVE = 2.5V NUMBER OF OCCURENCES Figure 49. Histogram of Codes—No OS (Six Codes) 1400 OVERSAMPLING BY 2 FSAMPLE = 100kSPS 1200 AVCC = 5V VDRIVE = 2.5V 2 –1 Figure 52.
PAGE 31
Data Sheet AD7606/AD7606-6/AD7606-4 –60 –70 –90 –100 100 –40 –20 –50 –30 ATTENUATION (dB) –10 –60 10k 100k 1M 10M FREQUENCY (Hz) 08479-051 1k –20 –40 –50 –60 –70 –100 100 1k 10k 100k AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 64 –20 ATTENUATION (dB) –50 –60 –70 –80 1M 10M FREQUENCY (Hz) 08479-052 –90 100k –40 –50 –60 –70 –90 –100 100 0 AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS BY 8 –20 –50 –60 –70 –80 10k 100k 1M 10M 08479-053 –90 FREQUENCY (Hz) 10k 10
PAGE 32
AD7606/AD7606-6/AD7606-4 Data Sheet LAYOUT GUIDELINES The printed circuit board that houses the AD7606/AD7606-6/ AD7606-4 should be designed so that the analog and digital sections are separated and confined to different areas of the board. At least one ground plane should be used. It can be common or split between the digital and analog sections.
PAGE 33
Data Sheet AD7606/AD7606-6/AD7606-4 To ensure good device-to-device performance matching in a system that contains multiple AD7606/AD7606-6/AD7606-4 devices, a symmetrical layout between the AD7606/AD7606-6/ AD7606-4 devices is important. Figure 64 shows a layout with two AD7606/AD7606-6/AD7606-4 devices. The AVCC supply plane runs to the right of both devices, and the VDRIVE supply track runs to the left of the two devices.
PAGE 34
AD7606/AD7606-6/AD7606-4 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 65.
PAGE 35
Data Sheet AD7606/AD7606-6/AD7606-4 NOTES Rev.
PAGE 36
AD7606/AD7606-6/AD7606-4 Data Sheet NOTES ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08479-0-1/12(C) Rev.