Datasheet

AD7568
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted
Parameter Rating
V
DD
to DGND −0.3 V to +6 V
I
OUT1
to DGND −0.3 V to V
DD
+0.3 V
I
OUT2
to DGND −0.3 V to V
DD
+0.3 V
Digital Input Voltage to DGND −0.3 V to V
DD
+0.3 V
V
RFB
, V
REF
to DGND ±15 V
Input Current to Any Pin Except Supplies
1
±10 mA
Operating Temperature Range
Commercial Plastic (B Versions) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Power Dissipation (Any Package) to 75°C 250 mW
Derates above 75°C by 10 mW/°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1
Transient currents of up to 100 mA will not cause SCR latch-up.
PIN DESCRIPTION
Mnemonic Description
V
DD
Positive Power Supply. This is 5 V ± 5%.
DGND Digital Ground.
AGND Analog Ground
V
REFA
to V
REFH
DAC Reference Inputs.
R
FBA
to R
FBH
DAC Feedback Resistor Pins.
I
OUTA
to I
OUTH
DAC Current Output Terminals.
AGND This pin connects to the back gates of the current steering switches. It should be connected to the signal ground of the system.
CLKIN
Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on the clock
line to avoid timing issues.
FSIN Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When FSIN goes low, it
enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address bit is valid, the 12-bit DAC
data is transferred to the appropriate input latch on the sixteenth falling edge after FSIN
goes low.
SDIN
Serial Data Input. The device accepts a 16-bit word. The first bit (DB15) is the DAC MSB, with the remaining bits following.
Next comes the device address bit, A0. If this does not correspond to the logic level on Pin A0, the data is ignored. Finally
comes the three DAC select bits. These determine which DAC in the device is selected for loading.
SDOUT This shift register output allows multiple devices to be connected in a daisy-chain configuration.
A0
Device Address Pin. This input gives the device an address. If DB3 of the serial input stream does not correspond to this, the
data that follows is ignored and not loaded to any input latch. However, it will appear at SDOUT irrespective of this.
LDAC Asynchronous LDAC Input. When this input is taken low, all DAC latches are simultaneously updated with the contents of the
input latches.
CLR Asynchronous CLR Input. When this input is taken low, all DAC latch outputs go to zero.
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REV. C