Datasheet

AD7568
–3–
TIMING SPECIFICATIONS
Limit at Limit at
Parameter T
A
= +258CT
A
= –408C to +858C Units Description
t
1
100 100 ns min CLKIN Cycle Time
t
2
40 40 ns min CLKIN High Time
t
3
40 40 ns min CLKIN Low Time
t
4
30 30 ns min FSIN Setup Time
t
5
30 30 ns min Data Setup Time
t
6
5 5 ns min Data Hold Time
t
7
90 90 ns min FSIN Hold Time
t
8
2
70 70 ns max SDOUT Valid After CLKIN Falling Edge
t
9
40 40 ns min LDAC, CLR Pulse Width
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
8
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
CLKIN (I)
SDIN (I)
SDOUT (O)
DB15 DB0
DB15
DB0
FSIN (I)
LDAC, CLR
t
1
t
4
t
7
t
2
t
3
t
6
t
5
t
8
t
9
NOTES
1. AO IS HARDWIRED HIGH OR LOW.
Figure 1. Timing Diagram
(V
DD
= +5 V 6 5%; I
OUT1
= I
OUT2
= 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
1.6mA I
OL
+2.1V
I
OH
200µA
C
L
50pF
TO OUTPUT
PIN
Figure 2. Load Circuit for Digital Output
Timing Specifications
REV. C