Datasheet

–5–
REV.
3
AD7564
Timing Specifications
1
(T
A
= T
MIN
to T
MAX
unless otherwise noted)
Limit at Limit at
Parameter V
DD
= +3 V to +3.6 V V
DD
= +4.75 V to +5.25 V Units Description
t
1
180 100 ns min CLKIN Cycle Time
t
2
80 40 ns min CLKIN High Time
t
3
80 40 ns min CLKIN Low Time
t
4
50 30 ns min FSIN Setup Time
t
5
50 30 ns min Data Setup Time
t
6
10 5 ns min Data Hold Time
t
7
125 90 ns min FSIN Hold Time
t
8
2
100 70 ns max SDOUT Valid After CLKIN Falling Edge
t
9
80 40 ns min LDAC, CLR Pulse Width
NOTES
1
Not production tested. Guaranteed by characterization at initial product release. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed
from a voltage level of 1.6 V for a V
DD
of 5 V and from a voltage level 1.35 V for a V
DD
of 3.3 V.
2
t
8
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with a V
DD
of 5 V and 0.6 V or 2.1 V for a V
DD
of 3.3 V.
DB15
DB15
DB0
t
2
t
3
t
4
t
5
t
7
t
8
t
9
DB0
t
6
t
1
FSIN(I)
CLKIN(I)
SDIN(I)
SDOUT(O)
LDAC, CLR
Figure 1. Timing Diagram
1.6mA
+1.6V
200µA
C
L
50pF
TO OUTPUT
PIN
I
OL
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
B