Datasheet

AD7538
Rev. B | Page 5 of 16
TIMING DIAGRAM
CS
LDAC
WR
DATA
5V
0V
5V
0V
5V
0V
5V
0V
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURES FROM 10%
TO 90% OF 5V,
t
R
= t
F
= 20ns.
2. TIMING MEASUREMENT REFERENCE LEVEL IS .
3. IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR,
THEN IT MUST STAY LOW FOR
t
3
OR LONGER AFTER WR GOES HIGH.
V
IH
+ V
IL
2
t
1
t
6
t
5
t
2
t
3
t
4
01139-002
Figure 2. Timing Diagram