Datasheet
AD7528
REV. B –5–
Table I. Unipolar Binary Code Table
DAC Latch Contents Analog Output
MSB LSB (DAC A or DAC B)
1 1 1 1 1 1 1 1
–V
IN
255
256
1 0 0 0 0 0 0 1
–V
IN
129
256
1 0 0 0 0 0 0 0
–V
IN
128
256
=−
V
IN
2
0 1 1 1 1 1 1 1
–V
IN
127
256
0 0 0 0 0 0 0 1
–V
IN
1
256
0 0 0 0 0 0 0 0
–V
IN
0
256
= 0
Note: 1 LSB =
2
−8
()
V
IN
()
=
1
256
V
IN
()
Table II. Bipolar (Offset Binary) Code Table
DAC Latch Contents Analog Output
MSB LSB (DAC A or DAC B)
1 1 1 1 1 1 1 1
+V
IN
127
128
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
–V
IN
1
128
0 0 0 0 0 0 0 1
–V
IN
127
128
0 0 0 0 0 0 0 0
–V
IN
128
128
Note: 1 LSB =
2
−7
()
V
IN
()
=
1
128
V
IN
()
Table III. Recommended Trim Resistor
Values vs. Grade
Trim
Resistor J/A/S K/B/T L/C/U
R1; R3 1 k 500 200
R2; R4 330 150 82
V
IN
A
(± 10V)
AD7528
V
IN
B
(± 10V)
R
FB
B
AGND
V
DD
DB0
DB7
DATA
INPUTS
DAC A/
DAC B
CS
WR
DGND
CONTROL
LOGIC
INPUT
BUFFER
OUT B
LATCH
R4
1
DAC B
C2
2
R3
1
DAC A
LATCH
V
OUT
B
AGND
R
FB
A
OUT A
R2
1
C1
2
V
OUT
A
AGND
R1
1
NOTES:
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
2
C1, C2 PHASE COMPENSATION (10pF–15pF) IS REQUIRED WHEN
USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
Figure 4. Dual DAC Unipolar Binary Operation
(2 Quadrant Multiplication); See Table I
V
IN
A
(± 10V)
AD7528
V
IN
B
(± 10V)
R
FB
B
AGND
V
DD
DB0
DB7
DATA
INPUTS
DAC A/
DAC B
CS
WR
DGND
CONTROL
LOGIC
INPUT
BUFFER
OUT BLATCH
R4
1
DAC B
C2
3
R3
1
DAC A
LATCH
V
OUT
B
AGND
R
FB
A
OUT A
R2
1
C1
3
V
OUT
A
AGND
R1
1
A1
R7
2
10kV
R6
2
20kV
A2
R5
20kV
R11
5kV
AGND
R10
2
20kV
R9
2
10kV
A4
R8
20kV
R12
5kV
AGND
A3
NOTES:
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE III FOR RECOMMENDED VALUES.
ADJUST R1 FOR V
OUT
A = 0V WITH CODE 10000000 IN DAC A LATCH.
ADJUST R3 FOR V
OUT
B = 0V WITH CODE 10000000 IN DAC B LATCH.
2
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R6, R7 AND R9, R10.
3
C1, C2 PHASE COMPENSATION (10pF–15pF) MAY BE REQUIRED
IF A1/A3 IS A HIGH SPEED AMPLIFIER.
Figure 5. Dual DAC Bipolar Operation
(4 Quadrant Multiplication); See Table II