Datasheet

AD7475/AD7495
Rev. B | Page 8 of 24
TIMING EXAMPLE 1
With f
SCLK
= 20 MHz and a throughput of 1 MSPS, the cycle
time is t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 1 μs. With t
2
= 10 ns min, t
ACQ
is 365 ns. The 365 ns satisfies the requirement of 300 ns for t
ACQ
.
In
Figure 3, t
ACQ
comprises 2.5(1/f
SCLK
) + t
8
+ t
QUIET
, where t
8
=
45 ns. This allows a value of 195 ns for t
QUIET
, satisfying the
minimum requirement of 100 ns.
TIMING EXAMPLE 2
With f
SCLK
= 5 MHz and a throughput of 315 KSPS, the cycle
time is t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 3.174 μs. With t
2
= 10 ns min,
t
ACQ
is 664 ns. The 664 ns satisfies the requirement of 300 ns for
t
ACQ
. In Figure 3, t
ACQ
comprises 2.5(1/f
SCLK
) + t8 + t
QUIET
, where
t8 = 45 ns. This allows a value of 119 ns for t
QUIET
, satisfying the
minimum requirement of 100 ns. As in this example and with
other slower clock values, the signal may already be acquired
before the conversion is complete, but it is still necessary
to leave 100 ns minimum t
QUIET
between conversions. In
Example 2, the signal should be fully acquired at approximately
Point C in
Figure 3.
SCLK
1
5
13
15
SDATA
FOUR LEADING ZEROS
THREE-STATE
t
4
2
3
16
t
5
t
3
t
QUIET
t
CONVERT
t
2
THREE-STATE
DB11 DB10
DB2
DB0
t
6
t
7
t
8
14
0
0
00
B
DB1
01684-B-002
CS
4
Figure 2. Serial Interface Timing Diagram
SCLK
1
5
13
15
2
3
16
t
5
t
QUIET
t
CONVERT
t
2
t
6
t
8
14
B
45ns
t
ACQUISITION
12.5 (1/f
SCLK
)
10ns
1/THROUGHPUT
C
01684-B-003
CS
4
Figure 3. Serial Interface Timing Example
200 μ A
I
OL
200 μ A
I
OH
C
L
50pF
TO OUTPUT
PIN
1.6V
01684-B-004
Figure 4. Load Circuit for Digital Output Timing Specifications