Datasheet

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1 MSPS,12-Bit ADCs

AD7475/AD7495

Rev. B

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FEATURES AND APPLICATIONS

Fast throughput rate: 1 MSPS

Specified for V

of 2.7 V to 5.25 V

Low power:

4.5 mW max at 1 MSPS with 3 V supplies

10.5 mW max at 1 MSPS with 5 V supplies

Wide input bandwidth:

68 dB SNR at 300 kHz input frequency

Flexible power/serial clock speed management

No pipeline delays

High speed serial interface:

SPI™-/QSPI™-/MICROWIRE™-/DSP-compatible

On-board reference: 2.5 V (AD7495 only)

Standby mode: 1 μA max

8-lead MSOP and SOIC packages

Battery-powered systems

Personal digital assistants

Medical instruments

Mobile communications

Instrumentation and control systems

Data acquisition systems

Optical sensors

GENERAL DESCRIPTION

The AD7475/AD7495

are 12-bit, high speed, low power,

successive-approximation ADCs that operate from a single

2.7 V to 5.25 V power supply with throughput rates up to

1 MSPS. They contain a low noise, wide bandwidth track-and-

hold amplifier that can handle input frequencies above 1 MHz.

The conversion process and data acquisition are controlled

using

and the serial clock, allowing the devices to interface

with microprocessors or DSPs. The input signal is sampled on

the falling edge of

and conversion is initiated at this point.

The conversion time is determined by the SCLK frequency.

There are no pipeline delays associated with the part.

The AD7475/AD7495 use advanced design techniques to

achieve very low power dissipation at high throughput rates.

With 3 V supplies and a 1 MSPS throughput rate, the AD7475

consumes just 1.5 mA, while the AD7495 consumes 2 mA.

With 5 V supplies and 1 MSPS, the current consumption is

2.1 mA for the AD7475 and 2.6 mA for the AD7495.

The analog input range for the parts is 0 V to REF IN. The 2.5 V

reference for the AD7475 is applied externally to the REF IN

pin, while the AD7495 has an on-board 2.5 V reference.

Protected by U.S. Patent No. 6,681,332

FUNCTIONAL BLOCK DIAGRAMS

T/H

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

AD7475

GND

SCLK

CONTROL

LOGIC

SDATA

DRIVE

REF IN

T/H

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

AD7495

GND

SCLK

CONTROL

LOGIC

SDATA

DRIVE

BUF

2.5V

REFERENCE

REF OUT

01684-B-001

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD7475 offers 1 MSPS throughput rates with 4.5 mW

power consumption.

2. Single-supply operation with V

DRIVE

function. The

AD7475/AD7495 operate from a single 2.7 V to 5.25 V

supply. The V

DRIVE

function allows the serial interface

to connect directly to either 3 V or 5 V processor systems

independent of V

3. Flexible power/serial clock speed management. The con-

version rate is determined by the serial clock, allowing the

conversion time to be reduced through the serial clock

speed increase. The parts also feature shutdown modes to

maximize power efficiency at lower throughput rates. This

allows the average power consumption to be reduced while

not converting. Power consumption is 1 μA when in full

shutdown.

4. No pipeline delay. The parts feature a standard successive

approximation ADC with accurate control of the sampling

instant via a

input and once-off conversion control.

Summary of content (24 pages)

PAGE 1
MSPS,12-Bit ADCs AD7475/AD7495 FUNCTIONAL BLOCK DIAGRAMS FEATURES AND APPLICATIONS Fast throughput rate: 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low power: 4.5 mW max at 1 MSPS with 3 V supplies 10.5 mW max at 1 MSPS with 5 V supplies Wide input bandwidth: 68 dB SNR at 300 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface: SPI™-/QSPI™-/MICROWIRE™-/DSP-compatible On-board reference: 2.
PAGE 2
AD7475/AD7495 TABLE OF CONTENTS AD7475 Specifications..................................................................... 3 Operating Modes............................................................................ 16 AD7495 Specifications..................................................................... 5 Normal Mode.............................................................................. 16 Timing Specifications.......................................................................
PAGE 3
AD7475/AD7495 AD7475 SPECIFICATIONS VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1.
PAGE 4
AD7475/AD7495 Parameter POWER REQUIREMENTS VDD VDRIVE IDD 3 Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode Partial Power-Down Mode Full Power-Down Mode Power Dissipation Normal Mode (Operational) Partial Power-Down (Static) Full Power-Down A Version 1 B Version1 Unit 2.7/5.25 2.7/5.25 2.7/5.25 2.7/5.25 V min/max V min/max 750 2.1 1.5 450 100 1 750 2.1 1.5 450 100 1 μA typ mA max mA max μA typ μA max μA max Digital inputs = 0 V or VDRIVE VDD = 2.7 V to 5.
PAGE 5
AD7475/AD7495 AD7495 SPECIFICATIONS VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 6
AD7475/AD7495 Parameter POWER REQUIREMENTS VDD VDRIVE IDD Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode Partial Power-Down Mode Full Power-Down Mode Power Dissipation 3 Normal Mode (Operational) Partial Power-Down (Static) Full Power-Down A Version 1 B Version1 Unit 2.7/5.25 2.7/5.25 2.7/5.25 2.7/5.25 V min/max V min/max 1 2.6 2 650 230 1 1 2.6 2 650 230 1 mA typ mA max mA max μA typ μA max μA max Digital inputs = 0 V or VDRIVE VDD = 2.7 V to 5.
PAGE 7
AD7475/AD7495 TIMING SPECIFICATIONS 1 VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475), TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter fSCLK 2 tCONVERT tQUIET t2 t3 3 t4 t5 t6 t7 t8 4 t9 tPOWER-UP Limit at TMIN, TMAX 10 20 16 × tSCLK 800 100 10 22 40 0.4 tSCLK 0.
PAGE 8
AD7475/AD7495 TIMING EXAMPLE 1 TIMING EXAMPLE 2 With fSCLK = 20 MHz and a throughput of 1 MSPS, the cycle time is t2 + 12.5(1/fSCLK) + tACQ = 1 μs. With t2 = 10 ns min, tACQ is 365 ns. The 365 ns satisfies the requirement of 300 ns for tACQ. In Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 45 ns. This allows a value of 195 ns for tQUIET, satisfying the minimum requirement of 100 ns. With fSCLK = 5 MHz and a throughput of 315 KSPS, the cycle time is t2 + 12.5(1/fSCLK) + tACQ = 3.174 μs.
PAGE 9
AD7475/AD7495 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Table 4.
PAGE 10
AD7475/AD7495 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF IN 1 8 VDD AD7475 7 CS TOP VIEW GND 3 (Not to Scale) 6 VDRIVE 5 SDATA SCLK 4 01684-B-005 VIN 2 Figure 5. AD7475 SOIC/MSOP Pin Configuration REF OUT 1 8 VDD AD7495 7 CS TOP VIEW GND 3 (Not to Scale) 6 VDRIVE SCLK 4 5 SDATA 01684-B-006 VIN 2 Figure 6. AD7495 SOIC/MSOP Pin Configuration Table 5. Pin Descriptions Pin No.
PAGE 11
AD7475/AD7495 TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental.
PAGE 12
AD7475/AD7495 TYPICAL PERFORMANCE CURVES Figure 7 shows a typical FFT plot for the AD7475 at a 1 MHz sample rate and a 100 kHz input frequency. 8192 POINT FFT fSAMPLE = 1MSPS fIN = 100kHz SINAD = 70.46dB THD = –87.7dB SFDR = –89.5dB –15 –35 71.0 VDD = VDRIVE = 4.75V 70.5 VDD = VDRIVE = 3.60V –55 SINAD (dB) SINAD (dB) Figure 9 shows the SINAD performance vs. input frequency for various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz. –75 70.0 VDD = VDRIVE = 2.70V 69.
PAGE 13
AD7475/AD7495 THEORY OF OPERATION The AD7475/AD7495 also feature power-down options to allow power saving between conversions. The power-down feature is implemented across the standard serial interface, as described in the Operating Modes section. CONVERTER OPERATION The AD7475/AD7495 are 12-bit, successive approximation analog-to-digital converters based around a capacitive DAC. The AD7475/AD7495 can convert analog input signals in the range 0 V to 2.5 V.
PAGE 14
AD7475/AD7495 TYPICAL CONNECTION DIAGRAM Analog Input Figure 13 and Figure 15 show typical connection diagrams for the AD7475 and AD7495, respectively. In both setups the GND pin is connected to the analog ground plane of the system. In Figure 13, REF IN is connected to a decoupled 2.5 V supply from a reference source, the AD780, to provide an analog input range of 0 V to 2.5 V. Although the AD7475 is connected to a VDD of 5 V, the serial interface is connected to a 3 V microprocessor.
PAGE 15
AD7475/AD7495 When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 16 shows a graph of the total harmonic distortion vs. source impedance for various analog input frequencies.
PAGE 16
AD7475/AD7495 OPERATING MODES The AD7475/AD7495 operating mode is selected by controlling the logic state of the CS signal during a conversion. There are three possible modes of operation: normal mode, partial powerdown mode, and full power-down mode. The point at which CS is pulled high after the conversion has been initiated determines which power-down mode, if any, the device enters.
PAGE 17
AD7475/AD7495 To exit this operating mode and power up the AD7475/AD7495 again, a dummy conversion is performed. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the tenth SCLK. The device is fully powered up once 16 SCLKs have elapsed, and valid data results from the next conversion, as shown in Figure 21.
PAGE 18
AD7475/AD7495 Full power-down is entered in a way similar to partial powerdown, except the timing sequence shown in Figure 20 must be executed twice. The conversion process must be interrupted in a similar fashion by bringing CS high anywhere after the second falling edge of SCLK and before the tenth falling edge of SCLK. The device enters partial power-down at this point. To reach full power-down, the next conversion cycle must be interrupted in the same way, as shown in Figure 22.
PAGE 19
AD7475/AD7495 POWER VS. THROUGHPUT RATE By using the partial power-down mode on the AD7475/ AD7495 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 24 shows how, as the throughput rate is reduced, the part remains in its partial power-down state longer and the average power consumption over time drops accordingly. 100 AD7495 5V SCLK = 20MHz AD7475 3V SCLK = 20MHz AD7495 3V SCLK = 20MHz 0.1 0.
PAGE 20
AD7475/AD7495 SERIAL INTERFACE Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7475/AD7495. CS going low provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges beginning with the second leading zero; thus the first falling clock edge on the serial clock has the second leading zero provided.
PAGE 21
AD7475/AD7495 MICROPROCESSOR INTERFACING AD7475/AD7495 TO TMS320C5X/C54X The serial interface on the TMS320C5x/C54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7475/AD7495. The CS input allows easy interfacing between the TMS320C5x/C54x and the AD7475/AD7495 without any glue logic required.
PAGE 22
AD7475/AD7495 For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, an SCLK of 2 MHz is obtained, and eight master clock periods elapse for every one SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling because the transmit instruction is occurring on a SCLK edge.
PAGE 23
AD7475/AD7495 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 4 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 0.50 (0.0196) × 45° 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.
PAGE 24
AD7475/AD7495 ORDERING GUIDE Model AD7475AR AD7475AR-REEL AD7475AR-REEL7 AD7475BR AD7475BR-REEL AD7475BR-REEL7 AD7475ARM AD7475ARM-REEL AD7475ARM-REEL7 AD7475BRM AD7475BRM-REEL AD7475BRM-REEL7 AD7475BRMZ3 AD7475BRMZ-REEL3 AD7475BRMZ-REEL73 AD7495AR AD7495AR-REEL AD7495AR-REEL7 AD7495BR AD7495BR-REEL AD7495BR-REEL7 AD7495BRZ 3 AD7495BRZ-REEL3 AD7495BRZ-REEL73 AD7495ARM AD7495ARM-REEL AD7495ARM-REEL7 AD7495ARMZ3 AD7495ARMZ-REEL3 AD7495ARMZ-REEL73 AD7495BRM AD7495BRM-REEL AD7495BRM-REEL7 EVAL-AD7495CB 4 EVAL-A