Datasheet

AD7492
Rev. A | Page 6 of 24
TIMING SPECIFICATIONS
V
DD
= 2.7 V to 5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 3.
Limit at T
MIN
, T
MAX
Parameter AD7492/AD7492-4 AD7492-5
2
Unit Description
t
CONVERT
880 680 ns max
t
WAKEUP
20
3
20
3
μs max Partial Sleep Wake-Up Time
500 500 μs max Full Sleep Wake-Up Time
t
1
10 10 ns min
CONVST Pulse Width
t
2
10 10 ns max
CONVST to BUSY Delay, V
DD
= 5 V
40 N/A ns max
CONVST to BUSY Delay, V
DD
= 3 V
t
3
0 0 ns max
BUSY to
CS Setup Time
t
4
4
0 0 ns max
CS to RD Setup Time
t
5
20 20 ns min
RD Pulse Width
t
6
4
15 15 ns min
Data Access Time after Falling Edge of
RD
t
7
5
8 8 ns max
Bus Relinquish Time after Rising Edge of
RD
t
8
0 0 ns max
CS to RD Hold Time
t
9
120 120 ns min Acquisition Time
t
10
100 100 ns min Quiet Time
1
Sample tested @ 25°C to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V (see Figure 2).
2
The AD7492-5 is specified with V
DD
= 4.75 V to 5.25 V.
3
This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 μs, but there is no guarantee that the part
samples within 0.5 LSB of the true analog input value. Therefore, the user should not start conversion until after the specified time.
4
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V
5
t
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
7
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
1.6V
200µA
I
OL
TO OUTPUT
PIN
C
L
50pF
200µA
I
OH
0
1128-002
Figure 2. Load Circuit for Digital Output Timing Specifications