Datasheet

AD7492
Rev. A | Page 20 of 24
80C186 to AD7492 Interface
Figure 33 shows the AD7492 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. (The AD7492 occupies
one of these I/O spaces.) Each data transfer consumes two bus
cycles, one cycle to fetch data and the other to store data.
After the AD7492 has finished the conversion, the BUSY line
generates a DMA request to Channel 1 (DRQ1). Because of the
interrupt, the processor performs a DMA read operation that
resets the interrupt latch. Sufficient priority must be assigned to
the DMA channel to ensure that the DMA request is serviced
before the completion of the next conversion. This
configuration can be used with 6 MHz and 8 MHz 80C186
processors.
ADDRESS/DATA BUS
DATA BUS
1
ADDITIONAL PINS OMITTED FOR CLARITY.
R
S
Q
OPTIONAL
80C186
1
RD
DRQ1
ALE
AD0 TO AD15
A16 TO A19
AD7492
ADDRESS
DECODER
ADDRESS
LATCH
ADDRESS
BUS
BUSY
DB0 TO DB9
(DB11)
CONVST
CS
RD
01128-033
Figure 33. 80C186 to AD7492 Interface