Datasheet

AD7484
Rev. C | Page 16 of 20
Data must not be read from the AD7484 while a conversion is
taking place. For this reason, if operating the AD7484 at
throughput speeds greater than 2.5 MSPS, it is necessary to tie
both the
CS
pin and
RD
pin on the AD7484 low and use a
buffer on the data lines. This situation may also arise in the case
where a read operation cannot be completed in the time after
the end of one conversion and the start of the quiet period
before the next conversion.
The maximum slew rate at the input of the ADC must be
limited to 500 V/µs while
BUSY
is low to avoid corrupting the
ongoing conversion. In any multiplexed application where the
channel is switched during conversion, this is to happen as soon
as possible after the
Reading Data from the AD7484
BUSY
falling edge.
Data is read from the part via a 15-bit parallel data bus with the
standard
CS
and
RD
signals. The
CS
and
RD
signals are internally
gated to enable the conversion result onto the data bus. The data
lines D0 to D14 leave their high impedance state when both
CS
and
RD
are logic low. Therefore,
CS
can be permanently tied
logic low if required, and the
Figure 29
RD
signal used to access the
conversion result.
shows a timing specification called
t
QUIET
. This is the amount of time that must be left after any data
bus activity before the next conversion is initiated.
Writing to the AD7484
The AD7484 features a user accessible offset register. This allows
the bottom of the transfer function to be shifted by ±200 mV. This
feature is explained in more detail in the Offset/Overrange section.
To write to the offset register, a 15-bit word is written to the
AD7484 with the 12 LSBs containing the offset value in twos
complement format. The 3 MSBs must be set to 0. The offset
value must be within the range −1310 to +1310, corresponding
to an offset from −200 mV to +200 mV. The value written to the
offset register is stored and used until power is removed from the
device, or the device is reset. The value stored may be updated at
any time between conversions by another write to the device.
Table 9 shows some examples of offset register values and their
effective offset voltage. Figure 30 shows a timing diagram for
writing to the AD7484.
Table 9. Offset Register Examples
Code
(Decimal) D14 to D12
D11 to D0 (Twos
Complement)
Offset
(mV)
−1310 000 1010 1110 0010 −200
−512 000 1110 0000 0000 −78.12
[phone] 0000 +39.06
[phone] 1110 +200
Driving the
CONVST
To achieve the specified performance from the AD7484, the
Pin
CONVST
pin must be driven from a low jitter source. Because
the falling edge on the
( )
( )
2
2
1
log10dB
jIN
JITTER
tfπ
SNR
××
=
CONVST
pin determines the sampling
instant, any jitter that may exist on this edge appears as noise
when the analog input signal contains high frequency components.
The relationship between the analog input frequency (f
IN
), timing
jitter (t
j
), and resulting SNR is given by
For example, if the desired SNR due to jitter is 100 dB with a
maximum full-scale analog input frequency of 1.5 MHz, ignor-
ing all other noise sources, the result is an allowable jitter on the
CONVST
falling edge of 1.06 ps. For a 14-bit converter (ideal
SNR = 86.04 dB), the allowable jitter is greater than 1.06 ps, but
due consider-ation must be given to the design of the
Typical Connection
CONVST
circuitry to achieve 14-bit performance with large analog input
frequencies.
Figure 23 shows a typical connection diagram for the AD7484
operating in Parallel Mode 1. Conversion is initiated by a falling
edge on
CONVST
. When
CONVST
goes low, the
BUSY
signal
goes low, and at the end of conversion, the rising edge of
BUSY
is used to activate an interrupt service routine. The
CS
and
In
RD
lines are then activated to read the 14 data bits (15 bits if using
the overrange feature).
Figure 23, the V
DRIVE
pin is tied to DV
DD
, which results in
logic output levels being either 0 V or DV
DD
. The voltage applied to
V
DRIVE
controls the voltage value of the output logic signals. For
example, if DV
DD
is supplied by a 5 V supply and V
DRIVE
is supplied
by a 3 V supply, the logic output levels are either 0 V or 3 V. This
feature allows the AD7484 to interface to 3 V devices while still
enabling the ADC to process signals at a 5 V supply.
MICROCONTROLLER/
MICROPROCESSOR
RESET
PARALLEL
INTERFACE
MODE1
MODE2
WRITE
CLIP
NAP
STBY
D0 TO D13
CS
CONVST
RD
BUSY
C
BIAS
REFSEL
REFIN
REFOUT
VIN
AD7484
ADM809
V
DRIVE
DV
DD
AV
DD
0.1µF
DIGITAL
SUPPLY
4.75V TO 5.25V
10µF
1nF
+
0.1µF
0.1µF
+
47µF
ANALOG
SUPPLY
4.75V TO 5.25V
0V TO 2.5V
1nF
0.47µF
0.47µF
AD780 2.5V
REFERENCE
02642-023
Figure 23. Typical Connection Diagram