Datasheet

AD7476/AD7477/AD7478
Rev. F | Page 18 of 24
SERIAL INTERFACE
Sixteen serial clock cycles are required to perform the
conversion process and to access data from the AD7476/
AD7477/AD7478.
Figure 23, Figure 24, and Figure 25 show the detailed timing
diagrams for serial interfacing to the AD7476, AD7477, and
AD7478, respectively. The serial clock provides the conversion
clock and controls the transfer of information from the part
during conversion.
CS
going low provides the first leading zero to be read by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Thus, the first falling clock edge on the serial clock
has the first leading zero provided and also clocks out the
second leading zero. The final bit in the data transfer is valid on
the 16th falling edge, having clocked out on the previous (15th)
falling edge. In applications with a slower SCLK, it is possible to
read data on each SCLK rising edge, although the first leading
zero has to be read on the first SCLK falling edge after the
CS
falling edge. Therefore, the first rising edge of SCLK after the
CS
falling edge provides the second leading zero. The 15th
rising SCLK edge has DB0 provided or the final zero for the
AD7477 and AD7478. This may not work with most
microcontrollers/DSPs, but could possibly be used with FPGAs
and ASICs.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into hold mode,
takes the bus out of three-state, and samples the analog input at
this point. The conversion initiates and requires 16 SCLK cycles
to complete. Once 13 SCLK falling edges have elapsed, the
track-and-hold goes back into track on the next SCLK rising
edge as shown at Point B in , , and .
On the sixteenth SCLK falling edge, the SDATA line will go
back into three-state. If the rising edge of
Figure 23 Figure 24 Figure 25
CS
occurs before
16 SCLKs have elapsed, the conversion terminates and the
SDATA line goes back into three-state; otherwise, SDATA
returns to three-state on the 16th SCLK falling edge as shown in
, , and . Figure 23 Figure 24 Figure 25
SCLK
S
DAT
A
CS
12345 13141516
B
THREE-STATE
THREE-
STATE
Z ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0
t
1
t
2
t
3
t
4
t
7
t
5
t
6
t
8
t
QUIET
t
CONVERT
4 LEADING ZEROS
01024-023
Figure 23. AD7476 Serial Interface Timing Diagram
SCLK
S
DAT
A
CS
12345 13141516
B
THREE-STATE
THREE-
STATE
Z ZERO ZERO ZERO DB9 DB8 DB0 ZERO ZERO
t
1
t
2
t
3
t
4
t
7
t
5
t
6
t
8
t
QUIET
t
CONVERT
4 LEADING ZEROS 2 TRAILING ZEROS
0
1024-024
Figure 24. AD7477 Serial Interface Timing Diagram
SCLK
S
DAT
A
CS
1234 1213141516
B
THREE-STATE
THREE-
STATE
Z ZERO ZERO ZERO DB7 ZEROZERO ZERO ZERO
t
1
t
2
t
3
t
4
t
7
t
5
t
6
t
8
t
QUIET
t
CONVERT
4 LEADING ZEROS 4 TRAILING ZEROS8 BITS OF DATA
0
1024-025
Figure 25. AD7478 Serial Interface Timing Diagram