Datasheet

AD7476/AD7477/AD7478
Rev. F | Page 15 of 24
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1 10k1k10010
01024-016
THD (dB)
SOURCE IMPEDANCE (Ω)
f
IN
= 200kHz
f
IN
= 300kHz
f
IN
= 100kHz
f
IN
= 10kHz
V
DD
= 2.7V
f
S
= 605kSPS
Figure 16. THD vs. Source Impedance for Various Analog Input Frequencies
V
DD
= 2.35V
V
DD
= 5.25V
V
DD
= 2.7V
V
DD
= 4.75V
V
DD
= 3.6V
–
50
–90
–85
–80
–75
–70
–65
–60
–55
10k 1M100k
01024-017
THD (dB)
INPUT FREQUENCY (Hz)
Figure 17. THD vs. Analog Input Frequency, f
s
= 993 kSPS
V
DD
= 2.35V
V
DD
= 3.6V
–
72
–74
–76
–78
–80
–82
–84
10k 1M100k
01024-018
THD (dB)
INPUT FREQUENCY (Hz)
V
DD
= 4.75V
V
DD
= 5.25V
V
DD
= 2.7V
Figure 18. THD vs. Analog Input Frequency, f
s
= 605 kSPS
Digital Input
The digital input applied to the AD7476/AD7477/AD7478 is
not limited by the maximum ratings that limit the analog input.
Instead, the digital input applied can go to 7 V and is not
restricted by the V
DD
+ 0.3 V limit as on the analog input. For
example, if the AD7476/AD7477/AD7478 are operated with a
V
DD
of 3 V, then 5 V logic levels can be used on the digital input.
However, note that the data output on SDATA still has 3 V logic
levels when V
DD
= 3 V. Another advantage of SCLK and
CS
not
being restricted by the V
DD
+ 0.3 V limit is that power supply
sequencing issues are avoided. If
CS
or SCLK is applied before
V
DD
, there is no risk of latch-up as there is on the analog input
when a signal greater than 0.3 V is applied prior to V
DD
.
MODES OF OPERATION
Select the mode of operation of the AD7476/AD7477/AD7478
by controlling the (logic) state of the
CS
signal during a
conversion. The two possible modes of operation are normal
mode and power-down mode. The point at which
CS
is pulled
high after the conversion has been initiated determines whether
or not the AD7476/AD7477/AD7478 enters power-down mode.
Similarly, if already in power-down,
CS
can control whether the
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for
different application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance.
Users do not have to worry about power-up times with the
AD7476/AD7477/AD7478 remaining fully powered at all times.
Figure 19 shows the general diagram of the AD7476/AD7477/
AD7478 in normal mode.
The conversion is initiated on the falling edge of
CS
as de-
scribed in the section. To ensure the part
remains fully powered up at all times,
Serial Interface
CS
must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of
CS
. If
CS
is brought high any time after the tenth SCLK
falling edge, but before the sixteenth SCLK falling edge, the part
remains powered up, but the conversion terminates and SDATA
goes back into three-state. Sixteen serial clock cycles are
required to complete the conversion and access the complete
conversion result.
CS
may idle high until the next conversion or
may idle low until
CS
returns high sometime prior to the next
conversion (effectively idling
CS
low).
Once a data transfer is complete, (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
t
QUIET
, has elapsed by again bringing
CS
low.