Datasheet

AD7476A/AD7477A/AD7478A
Rev. F | Page 9 of 28
Timing Diagrams
TO OUTPUT
PIN
C
L
50pF
200
µ
A
I
OH
200 µ A
I
OL
1.6V
02930-002
Figure 2. Load Circuit for Digital Output Timing Specifications
Timing Example 1
Having f
SCLK
= 20 MHz and a throughput of 1 MSPS, a cycle
time of
t
2
+ 12.5 (1/f
SCLK
) + t
ACQ
= 1 µs
where:
t
2
= 10 ns min, leaving t
ACQ
to be 365 ns. This 365 ns satisfies the
requirement of 250 ns for t
ACQ
.
From Figure 4, t
ACQ
is comprised of
2.5 (1/f
SCLK
) + t
8
+ t
QUIET
where:
t
8
= 36 ns maximum. This allows a value of 204 ns for t
QUIET
,
satisfying the minimum requirement of 50 ns.
Timing Example 2
Having f
SCLK
= 5 MHz and a throughput is 315 kSPS yields a
cycle time of
t
2
+ 12.5 (1/f
SCLK
) + t
ACQ
= 3.174 µs
where:
t
2
= 10 ns min, this leaves t
ACQ
to be 664 ns. This 664 ns satisfies
the requirement of 250 ns for t
ACQ
.
From Figure 4, t
ACQ
is comprised of
2.5 (1/f
SCLK
) + t
8
+ t
QUIET
, t
8
= 36 ns maximum
This allows a value of 128 ns for t
QUIET
, satisfying the minimum
requirement of 50 ns.
In this example and with other, slower clock values, the signal
may already be acquired before the conversion is complete, but
it is still necessary to leave 50 ns minimum t
QUIET
between
conversions. In Example 2, acquire the signal fully at
approximately Point C in Figure 4.
CS
SCLK
SDATA
t
2
t
6
t
3
t
4
t
7
t
5
t
8
t
CONVERT
t
QUIET
ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0
B
THREE-STATETHREE-
STATE
Z
4 LEADING ZEROS
1 3 13 14 15 16
t
1
4 52
02930-003
Figure 3. AD7476A Serial Interface Timing Diagram
CS
SCLK
t
2
t
CONVERT
B
1 2 5 13 14 15 16
C
t
8
t
QUIET
t
ACQ
12.5(1/f
SCLK
)
1/THROUGHPUT
3 4
02930-004
Figure 4. Serial Interface Timing Example