Datasheet

AD7476A/AD7477A/AD7478A
Rev. F | Page 17 of 28
Table 8 provides typical performance data with various op amps
used as the input buffer for a 100 kHz input tone at room
temperature under the same setup conditions.
Table 8. AD7476A Typical Performance with Various Input
Buffers, V
DD
= 3 V
Op Amp in the Input Buffer AD7476A SNR Performance (dB)
AD711 72.3
AD797 72.5
AD845 71.4
When no amplifier is used to drive the analog input, limit the
source impedance to low values. The maximum source imped-
ance depends on the amount of total harmonic distortion (THD)
that can be tolerated. The THD increases as the source impedance
increases, degrading the performance (see Figure 13).
DIGITAL INPUTS
The digital inputs applied to the AD7476A/AD7477A/AD7478A
are not limited by the maximum ratings that limit the analog
input. Instead, the digital inputs applied can reach 7 V and are
not restricted by the V
DD
+ 0.3 V limit as on the analog input.
For example, if operating the AD7476A/AD7477A/AD7478A
with a V
DD
of 3 V, u s e 5 V logic levels on the digital inputs.
However, note that the data output on SDATA still has 3 V logic
levels when V
DD
= 3 V. Another advantage of SCLK and
CS
not
being restricted by the V
DD
+ 0.3 V limit is that power supply
sequencing issues are avoided. If
CS
or SCLK are applied before
V
DD
, there is no risk of latch-up as there would be on the analog
input if a signal greater than 0.3 V were applied prior to V
DD
.