Datasheet

AD7476A/AD7477A/AD7478A
Rev. F | Page 11 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
6
5
4
1
2
3
V
DD
GND
V
IN
CS
SDATA
SCLK
AD7476A/
AD7477A/
AD7478A
02930-005
Figure 5. 6-Lead SC70 Pin Configuration
8
7
6
5
1
2
3
4
NC = NO CONNECT
V
DD
SDATA
V
IN
GND
SCLK
NCNC
TOP VIEW
(Not to Scale)
AD7476A/
AD7477A/
AD7478A
CS
02930-006
Figure 6. 8-Lead MSOP Pin Configuration
Table 6. Pin Function Descriptions
Mnemonic Description
CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7476A/AD7477A/AD7478A and also frames the serial data transfer.
V
DD
Power Supply Input. The V
DD
range for AD7476A/AD7477A/AD7478A is from 2.35 V to 5.25 V.
GND
Analog Ground. Ground reference point for all circuitry on AD7476A/AD7477A/AD7478A. Refer all analog input signals to this
GND voltage.
V
IN
Analog Input. Single-ended analog input channel. The input range is 0 V to V
DD
.
SDATA
Data Out. Logic output. The conversion result from AD7476A/AD7477A/AD7478A is provided on this output as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476A consists of four
leading zeros followed by 12 bits of conversion data that are provided MSB first. The data stream from the AD7477A consists
of four leading zeros followed by 10 bits of conversion data followed by two trailing zeros, provided MSB first. The data stream
from the AD7478A consists of four leading zeros followed by 8 bits of conversion data followed by four trailing zeros that are
provided MSB first.
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the
clock source for the conversion process of AD7476A/AD7477A/AD7478A.
NC No Connect.