Datasheet

AD7476A/AD7477A/AD7478A
Rev. F | Page 22 of 28
CS
going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the
second leading zero. Thus, the first falling clock edge on the
serial clock has the first leading zero provided and also clocks
out the second leading zero. For the AD7476A, the final bit in
the data transfer is valid on the 16th falling edge, having been
clocked out on the previous (15th) falling edge.
In applications with a slower SCLK, it is possible to read in data
on each SCLK rising edge. In this case, the first falling edge of
SCLK clocks out the second leading zero, which can be read in
the first rising edge. However, the first leading zero that was
clocked out when
CS
went low will be missed, unless it was not
read in the first falling edge. The 15th falling edge of SCLK clocks
out the last bit and it can be read in the 15th rising SCLK edge.
If
CS
goes low just after one SCLK falling edge has elapsed,
CS
clocks out the first leading zero as it did before, and it can be
read in the SCLK rising edge. The next SCLK falling edge clocks
out the second leading zero, and it can be read in the following
rising edge.
AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE
For the AD7478A, if
CS
is brought high in the 12th rising edge
after four leading zeros and eight bits of the conversion have
been provided, the part can achieve a 1.2 MSPS throughput
rate. For the AD7478A, the track-and-hold goes back into track
in the 11th rising edge. In this case, a f
SCLK
= 20 MHz and a
throughput of 1.2 MSPS give a cycle time of
t
2
+ 10.5(1/f
SCLK
)+ t
ACQ
= 833 ns
With t
2
= 10 ns min, this leaves t
ACQ
to be 298 ns. This 298 ns
satisfies the requirement of 225 ns for t
ACQ
.
From Figure 27, t
ACQ
is comprised of
0.5 (1/f
SCLK
) + t
8
+ t
QUIET
where t
8
= 36 ns maximum.
This allows a value of 237 ns for t
QUIET
, satisfying the minimum
requirement of 50 ns.
SCLK
t
1
1
5 11
SDATA
THREE-STATE
DB7
DB6
DB0
ZERO
ZERO
ZERO
4 LEADING ZEROS
2 3
t
2
t
8
12
1/THROUGHPUT
t
ACQ
10.5(1/ f
SCLK
)
t
CONVERT
t
QUIET
B
THREE-STATE
CS
4
02930-027
Z
Figure 27. AD7478A in a 12 SCLK Cycle Serial Interface