Datasheet

AD7476A/AD7477A/AD7478A
Rev. F | Page 8 of 28
TIMING SPECIFICATIONS
V
DD
= 2.35 V to 5.25 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 4.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
SCLK
2
10 kHz min
3
A, B grades
20 kHz min
3
Y grade
20 MHz max
t
CONVERT
16 × t
SCLK
AD7476A
14 × t
SCLK
AD7477A
12 × t
SCLK
AD7478A
t
QUIET
50 ns min Minimum quiet time required between bus relinquish
and start of next conversion
t
1
10 ns min
Minimum
CS
pulse width
t
2
10 ns min
CS
to SCLK setup time
t
3
4
22 ns max
Delay from
CS
until SDATA three-state disabled
t
4
4
40 ns max Data access time after SCLK falling edge
t
5
0.4 t
SCLK
ns min SCLK low pulse width
t
6
0.4 t
SCLK
ns min SCLK high pulse width
t
7
5
SCLK to data valid hold time
10 ns min V
DD
≤ 3.3 V
9.5 ns min 3.3 V < V
DD
≤ 3.6 V
7 ns min V
DD
> 3.6 V
t
8
6
36 ns max SCLK falling edge to SDATA high impedance
t
7
values also apply to t
8
minimum values ns min SCLK falling edge to SDATA high impedance
t
POWER-UP
7
1 μs max Power-up time from full power-down
1
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Minimum f
SCLK
at which specifications are guaranteed.
4
Measured with the load circuit shown in Figure 2, and defined as the time required for the output to cross 0.8 V or 1.8 V when V
DD
= 2.35 V, and
0.8 V or 2.0 V for V
DD
> 2.35 V.
5
Measured with a 50 pF load capacitor.
6
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. Therefore, the time, t
8
, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
7
See the Power-Up Time section.